View S3C84H5_7894029.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

S3C84H5/f84h5 8-bit cmos microcontrollers user's manual revision 1
important notice the information in this pub lication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. S3C84H5/f84h5 8-bit cmos microcontrollers user's manual, revision 1 publication number: 21-s3-c84h5/f84h5-012006 ? 2006 samsung electronics all rights reserved. no part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, giheung-eup yongin-city, gyeonggi-do, korea c.p.o. box #37, suwon 440-900 tel: (82)-(31)-209-5238 fax: (82)-(31)-209-6494 home page: http://www.samsung.com printed in the republic of korea
S3C84H5/f84h5 microcontroller iii preface the S3C84H5/f84h5 microcontroller user's manual is designed for application designers and programmers who are using the S3C84H5/f84h5 microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-rela ted information to familiarize you with the microcontroller's arch itecture, pr ogramming model, instruction set, and interrupt structure. it has six chapters: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 instruction set chapter 1, "product overview," is a high-level introduction to S3C84H5/f84h5 with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data memory spaces, the internal register file, and register addressing. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descriptions of the addressing modes that are supported by the s3c8-series cpu. chapter 4, "control registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in a standardized format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," describes the S3C84H5/f84h5 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in part ii. chapter 6, "instruction set," describes the features and conventions of the instruction set used for all s3c8-series microcontrollers. several summary tables are presented for orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruction when writing an application program. a basic familiarity with the information in part i will help you to understand the hardware modu le descriptions in part ii. if you are not yet familiar with the s3c8-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed information about specific hardware components of the S3C84H5/f84h5 microcontroller. also included in part ii are electrical, mechanical, otp, and development tools data. it has 17 chapters: chapter 7 clock circuit chapter 8 reset and power-down chapter 9 i/o ports chapter 10 basic timer chapter 11 8-bit timer a/b chapter 12 16-bit timer 1(0,1) chapter 13 10-bit pwm (pulse width modulation) chapter 14 serial i/o interface chapter 15 uart chapter 16 a/d converter chapter 17 watch timer chapter 18 lcd controller/driver chapter 19 low voltage reset chapter 20 embedded flash memory interface chapter 21 electrical data chapter 22 mechanical data chapter 23 development tools two order forms are included at th e back of this manual to facilitat e customer order for S3C84H5/f84h5 microcontrollers: the mask rom order form, and the mask option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative.
S3C84H5/f84h5 microcontroller v table of contents part i ? programming model chapter 1 product overview s3c8-series microcontrollers 1-1 S3C84H5/f84h5 microcontroller 1-1 features 1-2 block diagram 1-3 pin assignment 1-4 pin assignment 1-5 pin assignment 1-6 pin descriptions 1-7 pin circuits 1-11 chapter 2 address spaces overview 2-1 program memory (rom) 2-2 register architecture 2-4 register page pointer (pp) ..................................................................................................... .............2-6 register set 1 ................................................................................................................. ......................2-8 register set 2 ................................................................................................................. ......................2-8 prime register space........................................................................................................... ................2-9 working registers .............................................................................................................. ..................2-10 using the register pointers.................................................................................................... ..............2-11 register addressing 2-13 common working register area (c0h?cfh) .....................................................................................2-15 4-bit working register addressing .............................................................................................. ........2-16 8-bit working register addressing .............................................................................................. ........2-18 system and user stack 2-20 chapter 3 addressing modes overview 3-1 register addressing mode (r) 3-2 indirect register addressing mode (ir) 3-3 indexed addressing mode (x) 3-7 direct address mode (da) 3-10 indirect address mode (ia) 3-12 relative address mode (ra) 3-13 immediate mode (im) 3-14
vi S3C84H5/f84h5 microcontroller table of contents (continued) chapter 4 control registers overview 4-1 chapter 5 interrupt structure overview 5-1 interrupt types ................................................................................................................ ..................... 5-2 S3C84H5/f84h5 interrupt structure .............................................................................................. ..... 5-3 interrupt vector addresses ..................................................................................................... ............. 5-5 enable/disable interrupt instructions (ei, di) ................................................................................. ..... 5-7 system-level interrupt control registers....................................................................................... ..... 5-7 interrupt processing control points ............................................................................................ ......... 5-8 peripheral interrupt control registers ......................................................................................... ........ 5-9 system mode register (sym) ..................................................................................................... ........ 5-10 interrupt mask register (imr) .................................................................................................. ........... 5-11 interrupt priority register (ipr).............................................................................................. .............. 5-12 interrupt request register (irq)............................................................................................... .......... 5-14 interrupt pending function types............................................................................................... ......... 5-15 interrupt source polling sequen ce ................ .................. .................. .............. ............... ............. ........ 5-16 interrupt service routines ..................................................................................................... .............. 5-16 generating interrupt vector addresses .......................................................................................... ..... 5-17 nesting of vectored interrupts ................................................................................................. ............ 5-17 chapter 6 instruction set overview 6-1 data types..................................................................................................................... ...................... 6-1 register addressing ............................................................................................................ ................ 6-1 addressing modes ............................................................................................................... ................ 6-1 flags register (flags)......................................................................................................... .............. 6-6 flag descriptions .............................................................................................................. ................... 6-7 instruction set notation....................................................................................................... ................. 6-8 condition codes ................................................................................................................ .................. 6-12 instruction descriptions....................................................................................................... ................. 6-13
S3C84H5/f84h5 microcontroller vii table of contents (continued) part ii hardware descriptions chapter 7 clock circuit overview 7-1 system clock circuit ........................................................................................................... ..................7-1 clock status during power-down modes ........................................................................................... .7-2 system clock control register (clkcon) ......................................................................................... .7-3 chapter 8 reset and power-down system reset ................................................................................................................... .............................8-1 overview ....................................................................................................................... ........................8-1 normal mode reset operation.................................................................................................... .........8-1 hardware reset values.......................................................................................................... ..............8-2 power-down modes ............................................................................................................... .......................8-5 stop mode ...................................................................................................................... ......................8-5 idle mode ...................................................................................................................... ........................8-6 chapter 9 i/o ports overview 9-1 port data registers ............................................................................................................ ..................9-2 port 0 ......................................................................................................................... ...........................9-3 port 1 ......................................................................................................................... ...........................9-4 port 2 ......................................................................................................................... ...........................9-8 port 3 ......................................................................................................................... ...........................9-12 chapter 10 basic timer overview 10-1 basic timer (bt)............................................................................................................... ....................10-1 basic timer control register (btcon) ........................................................................................... ....10-1 basic timer function description............................................................................................... ..........10-3
viii S3C84H5/f84h5 microcontroller table of contents (continued) chapter 11 8-bit timer a/b 8-bit timer a 11-1 overview ....................................................................................................................... ....................... 11-1 function description ........................................................................................................... ................. 11-2 timer a control register (tacon) ............................................................................................... ...... 11-3 block diagram.................................................................................................................. .................... 11-4 8-bit timer b 11-5 overview ....................................................................................................................... ....................... 11-5 block diagram.................................................................................................................. .................... 11-5 timer b control register (tbcon) ............................................................................................... ...... 11-6 timer b pulse width calculations ............................................................................................... ........ 11-7 chapter 12 16-bit timer 1(0, 1) overview 12-1 function description ........................................................................................................... ................. 12-2 timer 1(0,1) control register (t1con0, t1con1) ............................................................................ 12-3 block diagram.................................................................................................................. .................... 12-6 chapter 13 10-bit pwm (pulse width modulation) overview 13-1 function description 13-1 pwm ............................................................................................................................ ........................ 13-1 pwm control register (pwmcon).................................................................................................. ... 13-5 chapter 14 serial i/o interface overview 14-1 programming procedure.......................................................................................................... ............ 14-1 serial i/o control registers (siocon) .......................................................................................... ..... 14-2 sio prescaler register (siops)................................................................................................. ......... 14-3
S3C84H5/f84h5 microcontroller ix table of contents (continued) chapter 15 uart overview 15-1 programming procedure .......................................................................................................... ............15-1 uart control register (uartcon) ................................................................................................ ...15-2 uart interrupt pending register (uartpnd)....................................................................................15 -4 uart data register (udata) ..................................................................................................... ........15-5 uart baud rate data register (brdatah, brdatal) ...................................................................15-6 baud rate calculations ......................................................................................................... ...............15-6 block diagram 15-8 uart mode 0 function description ............................................................................................... ......15-9 uart mode 1 function description ............................................................................................... ......15-10 uart mode 2 function description ............................................................................................... ......15-11 serial communication for multiprocessor configurations ....................................................................15-13 chapter 16 a/d converter overview 16-1 function description 16-1 a/d converter control register (adcon) ......................................................................................... ..16-2 internal reference voltage levels .............................................................................................. .........16-4 conversion timing .............................................................................................................. ...................16-4 internal a/d conversion procedure.............................................................................................. ........16-5 chapter 17 watch timer overview....................................................................................................................... .................................17-1 watch timer control register (wtcon: r/w) ....................................................................................17 -2 watch timer circuit diagram .................................................................................................... ...........17-3 chapter 18 low voltage reset overview....................................................................................................................... .................................18-1
x S3C84H5/f84h5 microcontroller table of contents (continued) chapter 19 mtp overview 19-1 chapter 20 electrical data overview ....................................................................................................................... ................................ 20-1 chapter 21 mechanical data overview ....................................................................................................................... ................................ 21-1 chapter 22 development tools overview 22-1 shine .......................................................................................................................... ........................ 22-1 sasm ........................................................................................................................... ........................ 22-1 sama assembler ................................................................................................................. ................ 22-1 hex2rom ........................................................................................................................ ................... 22-1 target boards .................................................................................................................. .................... 22-2 tb84h5 target board............................................................................................................ .............. 22-3 idle led ....................................................................................................................... ...................... 22-4 stop led ....................................................................................................................... .................... 22-4
S3C84H5/f84h5 microcontroller xi list of figures figure title page number number 1-1 S3C84H5/f84h5 block diagram1-3 1-2 S3C84H5/f84h5 pin assignment (32-pin sop/sdip) 1-4 1-3 S3C84H5/f84h5 pin assignment (30-pin sdip) 1-5 1-4 S3C84H5/f84h5 pin assignment (28-pin sop)1-6 1-5 pin circuit type b (nreset) 1-11 1-6 pin circuit type c 1-11 1-7 pin circuit type d 1-12 1-8 pin circuit type d-5 (p1.0~p1.3) 1-12 1-9 pin circuit type e(p2.2~p2.3,p1.4~1.5)1-13 1-10 pin circuit type g (p3.0-p3.4) 1-14 2-1 program memory address space 2-2 2-2 smart option 2-3 2-3 internal register file organization2-5 2-4 register page pointer (pp) 2-6 2-5 set 1, set 2, prime area register 2-9 2-6 8-byte working register areas (slices) 2-10 2-7 contiguous 16-byte working register block 2-11 2-8 non-contiguous 16-byte working register block 2-12 2-9 16-bit register pair 2- 13 2-10 register file addressing 2-14 2-11 common working register area2-15 2-12 4-bit working register addressing 2-17 2-13 4-bit working register addressing example 2-17 2-14 8-bit working register addressing 2-18 2-15 8-bit working register addressing example 2-19 2-16 stack operations 2 -20 3-1 register addressing 3-2 3-2 working register addressing3-2 3-3 indirect register addressing to register file3-3 3-4 indirect register addressing to program memory 3-4 3-5 indirect working register addressing to register file 3-5 3-6 indirect working register addressing to program or data memory 3-6 3-7 indexed addressing to register file 3-7 3-8 indexed addressing to program or data memory with short offset 3-8 3-9 indexed addressing to program or data memory3-9 3-10 direct addressing for load instructions 3-10 3-11 direct addressing for call and jump instructions 3-11 3-12 indirect addressing3 -12 3-13 relative addressing3- 13 3-14 immediate addressing3-14 4-1 register description format.......................................................................................4-4
xii S3C84H5/f84h5 microcontroller list of figures (continued) figure title page number number 5-1 s3c8-series interrupt types 5-2 5-2 S3C84H5/f84h5interrupt structure 5-4 5-3 rom vector address area 5-5 5-4 interrupt function diagram 5-8 5-5 system mode register (sym) 5-10 5-6 interrupt mask register (imr) 5-11 5-7 interrupt request priority groups 5-12 5-8 interrupt priority register (ipr) 5-13 5-9 interrupt request register (irq) 5-14 6-1 system flags register (flags) ............................................................................... 6-6 7-1 main oscillator circuit (crystal or ce ramic oscillator) 7-1 7-2 sub-system oscillator circuit (crystal oscillator) 7-1 7-3 system clock circuit diagram 7-2 7-4 system clock control register (clkcon) 7-3 7-5 oscillator control register (osccon) 7-4 7-6 stop control register (stopcon) 7-4 9-1 port 0 low byte control register (p0con) 9-3 9-2 port 1 high-byte control register (p1conh) 9-5 9-3 port 1 low-byte control register (p1conl) 9-6 9-4 port 1 interrupt pending register (p1intpnd) 9-7 9-5 port 1 interrupt enable register (p1int) 9-8 9-6 port 2 high-byte control register (p2conh) 9-9 9-7 port 2 low-byte control register (p2conl) 9-10 9-8 port 2 pull-up control register (p2pur) 9-11 9-9 port 3 low-byte control register (p3conl) 9-12 10-1 basic timer control register (btcon) 10-2 10-2 basic timer block diagram 10-4 11-1 timer a control register (tacon) 11-3 11-2 timer a functional block diagram 11-4 11-3 timer b functional block diagram 11-5 11-4 timer b control register (tbcon) 11-6 11-5 timer b data registers (tbdatah, tbdatal) 11-6 11-6 timer b output flip flop waveforms in repeat mode 11-8
S3C84H5/f84h5 microcontroller xiii list of figures (concluded) figure title page number number 12-1 timer 1(0,1) control register (t1con0, t1con1)12-4 12-2 timer a, timer 1(0,1) pending register (tintpnd) 12-5 12-3 timer 1(0,1) functional block diagram12-6 13-1 10-bit pwm basic waveform 13-3 13-2 10-bit extended pwm waveform13-4 13-3 pwm control register (pwmcon) 13-5 13-4 pwm functional block diagram13-6 14-1 serial i/o interface control register (siocon)14-2 14-2 sio pre-scaler register (siops) 14-3 14-3 sio functional block diagram 14-3 14-4 serial i/o timing in transmit-receive mode (tx at falling, siocon.4 = 0) 14-4 14-5 serial i/o timing in transmit-receive mode (tx at rising, siocon.4 = 1)14-4 14-6 serial i/o timing in receive-only mode 14-5 15-1 uart control register (uartcon) 15-3 15-2 uart interrupt pending register (uartpnd)15-4 15-3 uart data register (udata) 15-5 15-4 uart baud rate data register (brdatah, brdatal) 15-6 15-5 uart functional block diagram15-8 15-6 timing diagram for uart mode 0 operation 15-9 15-7 timing diagram for uart mode 1 operation 15-10 15-8 timing diagram for uart mode 2 operation 15-12 15-9 connection example for multiprocessor serial data communications 15-14 16-1 a/d converter control register (adcon) 16-2 16-2 a/d converter data register (addatah, addatal) 16-3 16-3 a/d converter circuit diagram16-3 16-4 a/d converter timing diagram 16-4 16-5 recommended a/d converter circuit for highest absolute accuracy 16-5 17-1 watch timer circuit diagram .....................................................................................17-3 18-1 low voltage reset circuit 18-2
xiv S3C84H5/f84h5 microcontroller list of figures (concluded) figure title page number number 19-1 pin assignment (32-pin sop/sdip) 19-1 19-2 pin assignment (30-pin sdip) 19-2 19-3 pin assignment (28-pin sop) 19-3 20-1 input timing for external interrupts (ports 2) 20-5 20-2 input timing for reset 20-5 20-3 clock timing measurement at x in 20-7 20-4 stop mode release timing initiated by reset 20-8 20-5 stop mode (main) release timing initiated by interrupts 20-9 20-6 stop mode (sub) release timing initiated by interrupts 20-9 20-7 waveform for uart timing characteristics 20-10 20-8 operating voltage range 20-12 20-9 the circuit diagram to improve eft characteristics 20-13 21-1 32-sop-450a package dimensions 21-1 21-2 32-sdip-400 package dimensions 21-2 21-3 30-pin sdip package dimensions 21-3 21-4 28-sop-375 package dimensions 21-4 22-1 smds+ or sk-1000 product configuration 22-2 22-2 s3f84i9/ s3f84i8/s3f84h5 target board configuration 22-3 22-3 44-pin connector pin assignment for tb84h5 22-5 22-4 42-pin connector pin assignment for tb84h5 22-6 22-5 tb84h5 adapter cable for 44pin connector package 22-6
S3C84H5/f84h5 microcontroller xv list of tables table title page number number 1-1 S3C84H5/f84h5 pin descriptions (32sop/32sdip/28sop)1-7 1-2 S3C84H5/f84h5 pin descriptions (30 sdip) 1-9 2-1 S3C84H5/f84h5 register type summary 2-4 4-1 set 1 registers 4-1 4-2 set 1, bank 0 registers4-2 4-3 set 1, bank 1 registers4-3 5-1 interrupt vectors 5 -6 5-2 interrupt control register overview 5-7 5-3 interrupt source control and data registers 5-9 6-1 instruction group summary6-2 6-2 flag notation conventions 6-8 6-3 instruction set symbols6-8 6-4 instruction notation conventions 6-9 6-5 opcode quick reference 6-10 6-6 condition codes 6- 12 8-1 S3C84H5/f84h5 set 1 register values after reset 8-2 8-2 S3C84H5/f84h5 set 1, bank 0 register values after reset 8-3 8-3 S3C84H5/f84h5 set 1, bank 1 register values after reset 8-4 9-1 S3C84H5/f84h5 port configuration overview9-1 9-2 port data register summary9-2 13-1 pwm control and data registers 13-2 13-2 pwm output "stretch" values for extension data register (pwmdatal .1?.0) 13-3 15-1 commonly used baud rates generated by 16bit brdata 15-7 17-1 watch timer control register (wtcon): set 1, bank 1, f8h, r/w 17-2 19-1 descriptions of pins used to read/write the flash rom19-4 19-2 comparison of s3f84h5 and S3C84H5 features19-4
xvi S3C84H5/f84h5 microcontroller list of tables table title page number number 20-1 absolute maximum ratings 20-2 20-2 input/output capacitance 20-2 20-3 d.c. electrical characteristics 20-3 20-4 a.c. electrical characteristics 20-5 20-5 main osc illator frequency (f osc1 ) 20-6 20-6 main oscillator cl ock stabilization time (t st1 ) 20-6 20-7 sub oscillator frequency (f osc2 ) 20-7 20-8 subsystem oscillator (crystal) stabilization time (t st2 ) 20-7 20-9 data retention supply voltage in stop mode 20-8 20-10 uart timing characteristics in mode 0 (10 mhz) 20-10 20-11 a/d converter electrical characteristics 20-11 20-12 lvr(low voltage reset) circuit characteristics 20-12 22-1 power selection settings for tb84h5 22-4 22-2 using single header pins as the input path for external trigger sources 22-4
S3C84H5/f84h5 microcontroller xvii list of programming tips description page number chapter 2: address spaces using the page pointer for ram clear 2-7 setting the register pointers 2-11 using the rps to calculate the sum of a series of registers 2-12 addressing the common working register area 2-16 standard stack operations using push and pop 2-21 chapter 9: i/o ports using the timer a 9-13 using ports 9-14 chapter 11: 8-bit timer a/b to generate 38 khz, 1/3duty signal through p2.0 11-9 to generate a one pulse signal through p2.0 11-10 using the timer a 11-11 using the timer b 11-12 chapter 12: 16-bit timer 1(0,1) using the timer 1(0) 12-7 chapter 13: 10-bit pwm (p ulse width modulation) programming the pwm module to sample specifications 13-7 chapter 14: serial i/o interface sio 14-5 chapter 16: a/d converter configuring a/d converter 16-6 chapter 17: watch timer using the watch timer 17-4
S3C84H5/f84h5 microcontroller xix list of register descriptions register full regi ster name page identifier number adcon a/d converter control register 4-5 btcon basic timer control register 4-6 clkcon system clock control register 4-7 flags system flags register 4-8 imr interrupt mask register 4-9 iph instruction pointer (high byte) 4-10 ipl instruction pointer (low byte) 4-10 ipr interrupt priority register 4-11 irq interrupt request register 4-12 osccon oscillator control register 4-13 p0con port 0 control register (high byte) 4-14 p1conh port 1 control register (high byte) 4-15 p1conl port 1 control register (low byte) 4-16 p1intpnd port 1 interrupt pending register 4-17 p1int port 1 interrupt enable 4- 18 p2conh port 2 control register (high byte) 4-19 p2conl port 2 control register (low byte) 4-20 p2pur port 2 pull-up resistor control register 4-21 p3conl port 3 control register (low byte) 4-22 pp register page pointer 4-23 pwmcon pwm control register 4-24 rp0 register pointer 0 4-25 rp1 register pointer 1 4-25 siocon serial i/o module control registers 4-26 siops sio prescaler register 4-27 sph stack pointer (high byte) 4-27 spl stack pointer (low byte) 4-27 stopcon stop control register 4-28 sym system mode register 4-29 t1con0 timer 1(0) control register 4-30 t1con1 timer 1(1) control register 4-31 tacon timer a control register 4-32 tbcon timer b control register 4-33 tintpnd timer a, timer 1 interrupt pending register 4-34 uartcon uart control register 4-35 uartpnd uart pending and parity control 4-37 wtcon watch timer control register 4-38
S3C84H5/f84h5 microcontroller xxi list of instruction descriptions instruction full regi ster name page mnemonic number adc add with carry 6-14 add add 6-15 and logical and 6-16 band bit and 6-17 bcp bit compare 6-18 bitc bit complement 6 -19 bitr bit reset 6-20 bitr bit reset 6-20 bits bit set 6-21 bor bit or 6-22 btjrf bit test, jump relative on false 6-23 btjrt bit test, jump relative on true 6-24 bxor bit xor 6-25 call call procedure 6-26 ccf complement carry flag 6-27 clr clear 6-28 com complement 6 -29 cp compare 6-30 cpije compare, increment, and jump on equal 6-31 cpijne compare, increment, and jump on non-equal 6-32 da decimal adjust 6- 33 da decimal adjust 6- 34 dec decrement 6-35 decw decrement word 6-3 6 di disable interrupts 6- 37 div divide (unsigned) 6- 38 djnz decrement and jump if non-zero 6-39 ei enable interrupts 6- 40 enter enter 6-41 exit exit 6-42 idle idle operation 6-43 inc increment 6-44 incw increment word 6- 45 iret interrupt return 6-46 jp jump 6-47 jr jump relative 6 -48 ld load 6-49 ld load 6-50 ldb load bit 6-51
xxii S3C84H5/f84h5 microcontroller list of instruction descriptions (continued) instruction full register name page mnemonic number ldc/lde load memory 6-52 ldc/lde load memory 6-53 ldcd/lded load memory and decrement 6-54 ldci/ldei load memory and increment6-55 `ldcpd/ldepd load memory with pre-decrement6-55 ldcpd/ldepd load memory with pre-decrement6-56 ldcpi/ldepi load memory with pre-increment 6-57 ldw load word 6-58 mult multiply (unsigned) 6 -59 next next 6-60 nop no operation 6-61 or logical or 6-62 pop pop from stack 6 -63 popud pop user stack (decrementing)6-64 popui pop user stack (incrementing) 6-65 push push to stack 6-66 pushud push user stack (dec rementing) 6-67 pushui push user stack (incrementing) 6-68 rcf reset carry flag6 -69 ret return 6-70 rl rotate left 6-71 rlc rotate left through carry 6-72 rr rotate right 6-73 rrc rotate right through carry6-74 sb0 select bank 0 6-75 sb1 select bank 1 6-76 sbc subtract with carry 6- 77 scf set carry flag 6-78 sra shift right arithmetic 6- 79 srp/srp0/srp1 set register pointer 6-80 stop stop operation 6-81 sub subtract 6-82 swap swap nibbles 6-83 tcm test complement under mask 6-84 tm test under mask 6-8 5 wfi wate for interrupt 6-86 xor logical exclusive or6-8 7
S3C84H5/f84h5 product overview 1-1 1 product overview s3c8-series microcontrollers samsung's s3c8-series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. the major cpu features are: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode released by interrupt or reset ? built-in basic timer wi th watchdog function a sophisticated interrupt structure recognizes up to eight-interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of four cpu clocks) can be assigned to specific interrupt levels. S3C84H5/f84h5 microcontroller the S3C84H5/f84h5 single-chip cmos microcontrollers are fabricated using the highly advanced cmos process technology based on samsung?s latest cpu architecture. the S3C84H5 is a microcontroller with a 16k-byte mask-programmable rom embedded. the s3f84h5 is a microcontroller with a 16k-byte flash rom embedded. using a proven modular design approach, samsung engineers have successfully developed the S3C84H5/f84h5 by integrating the following peripheral modules with the powerful sam8 core: ? five programmable i/o ports (32 sop/sdip: 22pins, 30 sdip: 20pins, 28 sop: 18pins) including ports shared with segment/common drive outputs. ? four bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stabiliza tion and watchdog func tion (system reset). ? two 8-bit timer/counter and two 16-bit timer/counter with selectable operating modes. ? one asynchronous uart and one synchronous sio ? one 10-bit pwm output ? 10-bit 8-channel a/d converter ? watch timer for real time the S3C84H5/f84h5 is versatile microcontroller for home appliances and adc applications, etc. they are currently available in 32 sop/sdip, 30 sdip, 28 sop package.
product overview S3C84H5/f84h5 1-2 features cpu ? sam8rc cpu core memory ? 272-bytes internal register file ? 16kbytes internal mult i time program memory oscillation sources ? main clock oscillator (crystal, ceramic) ? cpu clock divider (1/1, 1/2, 1/8, 1/16) instruction set ? 78 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 400 ns at 10-mhz f osc (minimum) interrupts ? 16 interrupt sources with 16 vectors. ? 8 level, 16 vector interrupt structure i/o ports ? total 22 bit-programmable pins (32 sop/sdip) total 20 bit-programmable pins (30 sdip) total 18 bit-programmable pins (28sop) timers and timer/counters ? one programmable 8-bit basic timer ( bt ) for oscillation stabilization co ntrol or watc hdog timer function. ? one 8-bit timer/counter ( timer a ) with three operating modes; interval mode, capture mode and pwm mode. ? one 8-bit timer ( timer b ) with carrier frequency (or pwm) generator. ? two 16-bit timer/counter ( timer 10,11) with three operating modes; interval mode, capture mode, and pwm mode. watch timer ? real-time and interval time measurement. ? four frequency output to buz pin. a/d converter ? 10-bit resolution ? eight-analog input channels ? 20us conversion speed at 10mhz f adc clock. asynchronous uart ? one asynchronous uart ? programmable baud rate generator ? supports serial data transmit/receive operations with 8-bit, 9-bit in uart pwm module ? one 10-bit programmable pwm output serial i/o ? one synchronous serial i/o module ? selectable transmit and receive rates built-in reset circuit (lvr) ? low-voltage check to make system reset ? v lvr = 2.8v (by smart option) oscillation frequency ? 1mhz to 10mhz external crystal oscillator operating temperature range ? -25 c to + 85 c operating voltage range ? lvr on : lvr to 5.5 v (8mhz) ? lvr off : 2.5 v to 5.5 v(8mhz) ? lvr off/on : 4.5 v to 5.5 v(10mhz) package type ? 32 pin sop/sdip, 30 pin sdip ? 28sop
S3C84H5/f84h5 product overview 1-3 block diagram adc0~adc7/ p0.0~p0.3 p1.4~p1.5 i/o port and interrupt control sam88rc cpu 16k-byte rom 528-byte ram osc/ resetb 8-bit basic timer 8-bit timer/counter a, b 16-bit timer/counter 10, 11 port 0 port 1 port 2 p2.0~p2.7/ t1ck0,t1cap0,t1out0 ad4,ad7,tbpwm,pwm si,so.sck,rxd,txd xin xout nreset p1.0/taout p1.2/tacap p1.1/tack p2.0/tbpwm p1.0~p1.5 int0~int3,buz,ad5,ad6 taout,tacap,tack t1out1,t1ck1,t1cap1 p0.0~p0.3 ad0~ad3 av ref av ss port 3 p3.0~p3.4 a/d uart p2.7/txd p2.6/rxd p2.2/t1out0 p2.0/t1ck0 p2.1/t1cap0 p1.3/t1out1 p1.4/t1ck1 p1.5/t1cap1 pwm sio p2.1/pwm p2.5/ sck p2.4/ so p2.3/ si xtin xtout p2.2~p2.3 figure 1-1. S3C84H5/f84h5 block diagram
product overview S3C84H5/f84h5 1-4 pin assignment v ss test xt in xt out nreset av ss p3.0 p3.1 ad0/p0.0 ad1/p0.1 ad2/p0.2 p0.3/ad3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 32-sop 32-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 p3.3 p3.2 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3 p1.2/tacap/int2 p1.1/tack/buz/int1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref figure 1-2. S3C84H5/f84h5 pin assignment (32-pin sop/sdip)
S3C84H5/f84h5 product overview 1-5 pin assignment v ss test xt in xt out nreset av ss p3.0 p3.1 ad0/p0.0 ad1/p0.1 p0.2/ad2 p0.3/ad3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 30-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3 p1.2/tacap/int2 p1.1/tack/buz/int1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref figure 1-3. S3C84H5/f84h5 pi n assignment (30-pin sdip)
product overview S3C84H5/f84h5 1-6 pin assignment v ss test xt in xt out nreset av ss ad0/p0.0 ad1/p0.1 ad2/p0.2 p0.3/ad3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 28-sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3 p1.2/tacap/int2 p1.1/tack/buz/int1 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref figure 1-4. S3C84H5/f84h5 pi n assignment (28-pin sop)
S3C84H5/f84h5 product overview 1-7 pin descriptions table 1-1. S3C84H5/f84h5 pin descriptions (32sop/32sdip/28sop) pin name pin type pin description circuit type pin number share pins p0.0?p0.3 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternately, can be used as ad0~ad3 e 14-17 (12-15) adc0, adc1, adc2, adc3 p1.0?p1.5 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternatively can be used as int0~int3, taout, tack, tacap, t1cap1, t1ck1, t1out1, ad5, ad6 d-5 e 22-23 28-31 (20-21 24-27) int0~int3 taout, tack tacap, t1ck1 t1cap1, ad5 t1out1, ad6, buz p2.0?p2.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, can be used as adc4,adc7,si t1cap0, t1out0, t1ck0, so, sck, rxd, txd tbpwm, pwm e d-5 10-13,18-21 (16-19 8-11) ad7 so, sck rxd, txd, t1cap0, t1cap1, t1ck0, pwm, tbpwm p3.0?p3.3 i/o bit programmable port; input or output mode selected by software; input or push-pull,n- channel open-drain output. software assignable pull-up. g 8-9, 26-27 note: pin numbers shown in parentheses "( )" are for the 28-pin sop package.
product overview S3C84H5/f84h5 1-8 table 1-1. S3C84H5/f84h5 pi n descriptions (continued) pin name pin type pin description circuit type pin number share pins int0?int3 i input pins for external interrupt. alternatively used as general-purpose digital input/output port 1 d-5 28-31 (24-27) p1.0?p1.3 adc0?adc7 i analog input pins for a/d converter module. alternatively used as general-purpose digital input/output port 0, port1 and port 2. e 14-17, 20-23, (12-5, 18-21) p0.0?p0.3 p2.2?p2.3 p1.4-p1.5 av ref , av ss ? a/d converter reference voltage and ground ? 24,25 (22,23) ? rxd i serial data rxd pin for receive input and transmit output (mode 0) e 12 (10) p2.6 txd o serial data txd pin for transmit output and shift clock output (mode 0) e 13 (11) p2.7 tack i external clock input pins for timer a d-5 29(25) p1.1 tacap i capture input pins for timer a d-5 30(26) p1.2 taout o pulse width modulation output pins for timer a d-5 28(24) p1.0 tbout o carrier frequency output pins for timer b d-5 18(16) p2.0 t1ck0 i external clock input pins for timer 1(0) d-5 18(16) p2.0 t1cap0 i capture input pins for timer 1(0) d-5 19(17) p2.1 t1out0 o timer 1(0) 16-bit pwm mode output or counter match toggle output pins d-5 20(18) p2.2 t1ck1 i external clock input pins for timer 1(1) e 22(20) p1.4 t1cap1 i capture input pins for timer 1(1) e 23(21) p1.5 t1out1 o timer 1(1) 16-bit pwm mode output or counter match toggle output pins e 31(27) p1.3 nreset i system reset pin b 7 ? test i pull-down resistor connected internally ? 4 ? v dd , v ss ? power input pins ? 1,32 ? xin, xout i,o main oscillator pins ? 2,3 ? note: pin numbers shown in parentheses "( )" are for the 28-pin sop package.
S3C84H5/f84h5 product overview 1-9 table 1-2. S3C84H5/f84h5 pin descriptions (30 sdip) pin name pin type pin description circuit type pin number share pins p0.0?p0.3 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternately, can be used as ad0~ad3 e 14-17 adc0, adc1, adc2, adc3 p1.0?p1.5 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternatively can be used as int0~int3, taout, tack, tacap, t1cap1, t1ck1, t1out1, ad5,ad6 d-5 e 22-23 26-29 int0~int3 taout, tack tacap,t1ck1 , t1cap1, ad5 t1out1, ad6, buz p2.0?p2.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, can be used as adc4, adc7, si, t1cap0, t1out0, t1ck0, so , sck, rxd, txd tbpwm, pwm e d-5 10-13, 18-21 adc6~adc7 so, sck rxd, txd, t1cap0, t1cap1, t1ck0, pwm, tbpwm p3.0?p3.3 i/o bit programmable port; input or output mode selected by software; input or push-pull, n-channel open-drain output. software assignable pull-up. g 8-9
product overview S3C84H5/f84h5 1-10 table 1-2. S3C84H5/f84h5 pi n descriptions (continued) pin name pin type pin description circuit type pin number share pins int0?int3 i input pins for external interrupt. alternatively used as general-purpose digital input/output port 1 d-5 26-29 p1.0?p1.3 adc0?adc7 i analog input pins for a/d converter module. alternatively used as general-purpose digital input/output port 0, port1 and port 2. e 14-17, 20-23 p0.0?p0.3 p2.2?p2.3 p1.4?p1.5 av ref , av ss ? a/d converter reference voltage and ground ? 24, 25 ? rxd i serial data rxd pin for receive input and transmit output (mode 0) e 12 p2.6 txd o serial data txd pin for transmit output and shift clock output (mode 0) e 13 p2.7 tack i external clock input pins for timer a d-5 27 p1.1 tacap i capture input pins for timer a d-5 28 p1.2 taout o pulse width modulation output pins for timer a d-5 26 p1.0 tbout o carrier frequency output pins for timer b d-5 18 p2.0 t1ck0 i external clock input pins for timer 1(0) d-5 18 p2.0 t1cap0 i capture input pins for timer 1(0) d-5 19 p2.1 t1out0 o timer 1(0) 16-bit pwm mode output or counter match toggle output pins d-5 20 p2.2 t1ck1 i external clock input pins for timer 1(1) e 22 p1.4 t1cap1 i capture input pins for timer 1(1) e 23 p1.5 t1out1 o timer 1(1) 16-bit pwm mode output or counter match toggle output pins e 29 p1.3 nreset i system reset pin b 7 ? test i pull-down resistor connected internally ? 4 ? v dd , v ss ? power input pins ? 1, 32 ? xin, xout i,o main oscillator pins ? 2, 3 ?
S3C84H5/f84h5 product overview 1-11 pin circuits schmitt trigger in v dd pull-up resistor figure 1-5. pin circuit type b (nreset) p-channel n-channel v dd out output disable data figure 1-6. pin circuit type c
product overview S3C84H5/f84h5 1-12 i/o output disable data pin circuit type c pull-up enable v dd figure 1-7. pin circuit type d i/o output disable port data pin circuit type c pull-up enable v dd ext.int normal input v dd m u x alternative output filter noise figure 1-8. pin circuit type d-5 (p1.0~p1.3)
S3C84H5/f84h5 product overview 1-13 v dd pull-up resistor (typical value:50k ? ) v dd pull-up enable normal input output disable in/out analog input port data m u x alternative output figure 1-9. pin circuit ty pe e(p2.2~p2.3,p1.4~1.5)
product overview S3C84H5/f84h5 1-14 i/o pull-up enable v dd normal input p-channel n-channel v dd output disable data open-drain figure 1-10. pin circui t type g (p3.0-p3.4)
S3C84H5/f84h5 address spaces 2-1 2 address spaces overview the S3C84H5/f84h5 microcontroller has two types of address space: ? internal program memory (rom) ? internal register file (ram) a 16-bit address bus supports program memory operations. a separate 8-bit register bus carries addresses and data between the cpu and the register file. the S3C84H5/f84h5 has an internal 16-kbyte mask-programmable rom / 16-kbyte flash rom and 272-byte ram.
address spaces S3C84H5/f84h5 2-2 program memory (rom) program memory (rom) stores program codes or table data. the S3C84H5/f84h5 has 16 kbytes of internal mask programmable program memory. th e program memory address range is therefor e 0h-3fffh (see figure 2-1). the first 256 bytes of the rom (0h-0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. the rom address at which a program execution starts after a reset is 0100h. internal program memory (flash) interrupt vector area smart option rom cell 16,383 (decimal) 255 0 00h 0ffh 3fffh (hex) 03ch 03fh s3f84h5(16kbyte) figure 2-1. program memory address space
S3C84H5/f84h5 address spaces 2-3 smart option smart option is the rom option for starting condition of the chip. the rom addresses used by smart option are from 003ch to 003fh. the default value of rom is ffh. note: the value of unused bits of 03ch,03dh,03eh and 03fh must be logic "1" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb rom address: 003fh lvr on-off control bit 0 = disable 1 = enable not used not used rom address: 003dh rom address: 003ch .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used .7 .6 .5 .4 .3 .2 .1 .0 msb lsb rom address: 003eh .7 .6 .5 .4 .3 .2 .1 .0 msb lsb not used figure 2-2. smart option
address spaces S3C84H5/f84h5 2-4 register architecture in the S3C84H5/f84h5 implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. in case of S3C84H5/f84h5 the total number of addressable 8-bit registers is 334. of these 334 registers, 13 bytes are for cpu and system control registers, 49 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers and 256 registers are for general-purpose use. you can always address set 1 register location, regardless of which of the 2 register pages is currently selected. the set 1 locations, however, can only be addressed using direct addressing modes. the extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, sb0 and sb1, and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the register file are summarized in table 2?1. table 2-1. S3C84H5/f84h5 register type summary register type number of bytes general-purpose registers (including 16-byte common working register area, expanded 2 separately addressable register pages (1page occupies 172-byte prime register area and the 64-byte set 2 area) cpu and system control registers mapped clock, peripheral, i/o control, and data registers 272 13 49 total addressable bytes 334
S3C84H5/f84h5 address spaces 2-5 ffh e0h e0h dfh d0h cfh c0h set1 c0h bfh 00h ffh ffh bank 1 system and peripheral control registers (register addressing mode) system and peripheral control registers (register addressing mode) general purpose register (register addressing mode) bank 0 page 0 set 2 general-purpose data registers (indirect register, indexed mode, and stack operations) prime data registers (all addressing modes) 32 bytes bytes 64 256 bytes 192 bytes figure 2-3. internal regi ster file organization
address spaces S3C84H5/f84h5 2-6 register page pointer (pp) the s3c8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 2 separately addressable register pages. page addressing is controlled by the register page pointer (pp, dfh). in the S3C84H5/f84h5 microcontroller, a paged register file expansion is implemented for data registers, and the register page pointer must be changed to address other pages. after a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. register page pointer (pp) dfh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 destination register page selection bits: destination: page 0 source register page selection bits: source: page 0 note: a hardware reset operation writes the 4-bit destination and source values shown above tho the register page pointer. these values should be modified to other page. 0000 0000 figure 2-4. register page pointer (pp)
S3C84H5/f84h5 address spaces 2-7 programming tip ? using the page pointer for ram clear ld pp,#00h ; destination 0, source 0 srp #0c0h ld r0,#0ffh ; page 0 ram clear starts ramcl0: clr @r0 djnz r0,ramcl0 clr @r0 ; r0 = 00h ld pp,#10h ; destination 1, source 0 ld r0,#0ffh ; page 1 ram clear starts ramcl1: clr @r0 djnz r0,ramcl1 clr @r0 ; r0 = 00h
address spaces S3C84H5/f84h5 2-8 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. the upper 32-byte area of this 64-byte space (e0h?ffh) is expanded two 32-byte register banks, bank 0 and bank 1 . the set register bank instructions, sb0 or sb1, are used to address one bank or the other. a hardware reset operation always selects bank 0 addressing. the upper two 32-byte areas (bank 0 and bank 1) of set 1 (e0h?ffh) contains 64 mapped system and peripheral control registers. the lower 32-byte area contains 16 system registers (d0h?dfh) and a 16-byte common working register area (c0h?cfh). you can use the common working register area as a ?scratch? area for data operations being performed in other areas of the register file. registers in set 1 locations are directly accessible at all times using register addressing mode. the 16-byte working register area can only be accessed using working register addressing (for more information about working register addressing, please refer to chapter 3, ?addressing modes.?) register set 2 the same 64-byte physical space that is used for set 1 locations c0h?ffh is logically duplicated to add another 64 bytes of register space. this expanded area of the register file is called set 2 . for S3C84H5/ f84h5, the set 2 address range (c0h?ffh) is accessible on pages 0-1. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. you can use only register addressing mode to access set 1 locations. in order to access registers in set 2, you must use register indirect addressing mode or indexed addressing mode. the set 2 register area is commonly used for stack operations.
S3C84H5/f84h5 address spaces 2-9 prime register space the lower 192 bytes (00h?bfh) of the S3C84H5/ f84h5's a 256-byte register pages is called prime register area. prime registers can be accessed using any of the seven addressing modes (see chapter 3, "addressing modes.") the prime register area on page 0 is immediately addressable following a reset. in order to address prime registers on pages, you must set the register page pointer (pp) to the appropriate source and destination values. ffh f0h e0h d0h c0h set 1 bank 0 peripheral and i/o general-purpose cpu and system control ffh c0h set 2 00h prime space bfh bank 1 page 0 figure 2-5. set 1, set 2, prime area register
address spaces S3C84H5/f84h5 2-10 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." each slice comprises of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slices can be selected at any one time to form a 16-byte working register block. using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit working registers, r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers, r0?r15) all the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2. the base addresses for the two selected 8-byte register slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to the 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16- byte working register block. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 slice 31 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 2 slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2-6. 8-byte working register areas (slices)
S3C84H5/f84h5 address spaces 2-11 using the register pointers register pointers rp0 and rp1, mapped to addresses d6h and d7h in set 1, are used to select two movable 8-byte working register slices in the register file. after a reset, rp# point to the working register common area: rp0 points to addresses c0h?c7h, and rp1 points to addresses c8h?cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction. (see figures 2-6 and 2-7). with working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by rp0 and rp1. you cannot, however, use the register pointers to select a working register space in set 2, c0h?ffh, because these locations can be accessed only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually consists of two contiguous 8-byte slices. as a general programming guideline, it is recommended that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). ). in some cases, it may be necessary to define working register areas in different (non- contiguous) areas of the register file. in figure 2-7, rp0 points to the "upper" slice and rp1 to the "lower" slice. because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. programming tip ? setting the register pointers srp #70h ; rp0 70h, rp1 78h srp1 #48h ; rp0 no change, rp1 48h, srp0 #0a0h ; rp0 0a0h, rp1 no change clr rp0 ; rp0 00h, rp1 no change ld rp1,#0f8h ; rp0 no change, rp1 0f8h fh (r15) 0h (r0) 8-byte slice 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice figure 2-7. contiguous 16-byt e working register block
address spaces S3C84H5/f84h5 2-12 16-byte non- contiguous working register bloc k register file contains 32 8-byte slices 8-byte slice 0h (r8) 7h (r15) f0h (r0) f7h (r7) rp1 rp0 1 1 1 1 0 x x x 0 0 0 0 0 x x x 8-byte slice figure 2-8. non-cont iguous 16-byte worki ng register block programming tip ? using the rps to calcul ate the sum of a series of registers calculate the sum of registers 80h?85h using the register pointer. the register addresses from 80h through 85h contain the values 10h, 11h, 12h, 13h, 14h, and 15 h, respectively: srp0 #80h ; rp0 80h add r0,r1 ; r0 r0 + r1 adc r0,r2 ; r0 r0 + r2 + c adc r0,r3 ; r0 r0 + r3 + c adc r0,r4 ; r0 r0 + r4 + c adc r0,r5 ; r0 r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. if the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: add 80h,81h ; 80h (80h) + (81h) adc 80h,82h ; 80h (80h) + (82h) + c adc 80h,83h ; 80h (80h) + (83h) + c adc 80h,84h ; 80h (80h) + (84h) + c adc 80h,85h ; 80h (80h) + (85h) + c now, the sum of the six registers is also located in register 80h. however, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.
S3C84H5/f84h5 address spaces 2-13 register addressing the s3c8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. working register addressing differs from register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space. msb rn lsb rn+1 n = even address figure 2-9. 16-bit register pair
address spaces S3C84H5/f84h5 2-14 rp1 rp0 register pointers 00h all addressing modes page 0 indirect register, indexed addressing modes page 0 register addressing only can be pointed by register pointer ffh e0h bfh control registers system registers special-purpose registers d0h c0h bank 1 bank 0 note: in the S3C84H5/f84h5 microcontroller, pages 0-1 are implemented. pages 0-1 contain all of the addressable registers in the internal register file. each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (that is, to the common working register area). ffh c0h set 2 cfh general-purpose register prime registers figure 2-10. register file addressing
S3C84H5/f84h5 address spaces 2-15 common working register area (c0h?cfh) after a reset, register pointers rp0 and rp1 automatically select two 8-byte register slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 c0h?c7h rp1 c8h?cfh this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the register file. typically, these working registers serve as temporary buffers for data operations between different pages. ffh f0h e0h d0h c0h set 1 ffh c0h set 2 00h prime space bfh page 0 page 0 following a hardware reset, register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh. rp0 = rp1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 ~ ~ figure 2-11. common work ing register area
address spaces S3C84H5/f84h5 2-16 programming tip ? addressing th e common working register area as the following examples show, you should access working registers in the common area, locations c0h?cfh, using working register addressing mode only. examples 1: ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) the value in location 40h example 2: add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) r3 + 45h 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of th e register pointers ("0" selects rp0, "1" selects rp1). ? the five high-order bits in the register pointer select an 8-byte slice of the register space. ? the three low-order bits of the 4-bit address select one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working register addressing. the high-order bit of the instruction "inc r6" is "0", which selects rp0. the five high-order bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit address (110b) to produce the register address 76h (01110110b).
S3C84H5/f84h5 address spaces 2-17 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address provides three low-order bits figure 2-12. 4-bit worki ng register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-13. 4-bit working re gister addressing example
address spaces S3C84H5/f84h5 2-18 8-bit working register addressing you can also use 8-bit working register addressing to access registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value "1100b." this 4-bit value (1100b) indicates that the remaining four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit addressing. bit 3 selects either rp0 or rp1, which then supplies the five high-order bits of the final address. the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addressing. the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bit 3 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the register address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five-address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit logical address 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low-order bits these address bits indicate 8-bit working register addressing 1100 figure 2-14. 8-bit worki ng register addressing
S3C84H5/f84h5 address spaces 2-19 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2-15. 8-bit working re gister addressing example
address spaces S3C84H5/f84h5 2-20 system and user stack the s3c8-series microcontrollers use the system stack for data storage, subroutine calls and returns. the push and pop instructions are used to control system stack operations. the S3C84H5/f84h5 architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls, interrupts, and data are stored on the stack. the contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags register are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address value is always decreased by one before a push operation and increased by one after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-16. stack operations user-defined stacks you can freely define stacks in the internal register file as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack pointer (sp) that is used for system stack operations. the most significant byte of the sp address, sp15?sp8, is stored in the sph register (d8h), and the least significant byte, sp7?sp0, is stored in the spl register (d9h). after a reset, the sp value is undetermined. because only internal memory space is implemented in th e s3c84i5/c84i9/f84i9, the spl must be initialized to an 8-bit value in the range 00h?ffh. the sph register is not needed and can be used as a general-purpose register, if necessary. when the spl register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the sph register as a general-purpose data register. however, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the spl register during normal stack operations, the value in the spl register will overflow (or underflow) to the sph register, overwriting any other data that is currently stored there. to avoid overwriting data in the sph register, you can initialize the spl value to "ffh" instead of "00h".
S3C84H5/f84h5 address spaces 2-21 programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operations in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ffh ; (normally, the spl is set to 0ffh by the initialization ; routine) ? ? ? push pp ; stack address 0feh pp push rp0 ; stack address 0fdh rp0 push rp1 ; stack address 0fch rp1 push r3 ; stack address 0fbh r3 ? ? ? pop r3 ; r3 stack address 0fbh pop rp1 ; rp1 stack address 0fch pop rp0 ; rp0 stack address 0fdh pop pp ; pp stack address 0feh
S3C84H5/f84h5 addressing modes 3-1 3 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam8rcinstructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c8-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the seven addressing modes and their symbols are: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im)
addressing modes S3C84H5/f84h5 3-2 register addressing mode (r) in register addressing mode (r), the operand value is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 ot rp1 figure 3-2. working register addressing
S3C84H5/f84h5 addressing modes 3-3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of th e specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3-6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. please note, however, that you cannot access locations c0h?ffh in set 1 using the indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file
addressing modes S3C84H5/f84h5 3-4 indirect register addr essing mode (continued) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory
S3C84H5/f84h5 addressing modes 3-5 indirect register addressing mode (continued) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start fo working register block rp0 or rp1 msb points to rp0 or rp1 ~~ ~~ figure 3-5. indirect working regist er addressing to register file
addressing modes S3C84H5/f84h5 3-6 indirect register addr essing mode (continued) dst opcode 4-bit working register address sample instructions: lcd r5,@rr6 ; program memory access lde r3,@rr14 ; external data memory access lde @rr4, r8 ; external data memory access program memory register file src value used in instruction operand example instruction references either program memory or data memory program memory or data memory next 2-bit point to working register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect worki ng register addressing to program or data memory
S3C84H5/f84h5 addressing modes 3-7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. please note, however, that you cannot access locations c0h?ffh in set 1 using indexed addressing mode. in short offset indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8.) for register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to that base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the woking register (1 of 8) sample instruction: ld r0, #base[r1] ; where base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block ~~ ~~ + figure 3-7. i ndexed addressing to register file
addressing modes S3C84H5/f84h5 3-8 indexed addressing mode (continued) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~~ figure 3-8. indexed addressing to program or data memory with short offset
S3C84H5/f84h5 addressing modes 3-9 indexed addressing mode (continued) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 16-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + ~~ figure 3-9. indexed addressing to program or data memory
addressing modes S3C84H5/f84h5 3-10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addres sing for load instructions
S3C84H5/f84h5 addressing modes 3-11 direct address mode (continued) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing fo r call and jump instructions
addressing modes S3C84H5/f84h5 3-12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indi rect addressing
S3C84H5/f84h5 addressing modes 3-13 relative address mode (ra) in relative address (ra) mode, a twos-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. rela tive addressing
addressing modes S3C84H5/f84h5 3-14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing
S3C84H5/f84h5 control register 4-1 4 control registers overview control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. the locations and read/write characteristics of all mapped registers in the S3C84H5/f84h5 register file are listed in table 4-1. the hardware reset value for each mapped register is described in chapter 8, ?reset and power- down." table 4-1. set 1 registers register name mnemonic decimal hex r/w timer b control register tbcon 208 d0h r/w timer b data register (high byte) tbdatah 209 d1h r/w timer b data register (low byte) tbdatal 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w
control registers S3C84H5/f84h5 4-2 table 4-2. set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w location e4h is not mapped stop control register stopcon 229 e5h r/w port 0 control register p0con 230 e6h r/w location e7h is not mapped port 1 control register (high byte) p1conh 232 e8h r/w port 1 control register (low byte) p1conl 233 e9h r/w port 1 interrupt pending register p1intpnd 234 eah r/w port 1 interrupt control register p1int 235 ebh r/w port 2 control register (high byte) p2conh 236 ech r/w port 2 control register (low byte) p2conl 237 edh r/w location eeh is not mapped port 3 control register (low byte) p3conl 239 efh r/w location f0h,f1h is not mapped oscillator control register osccon 242 f2h r/w location f3h is not mapped uart pending register uartpnd 244 f4h r/w uart data register udata 245 f5h r/w uart control register uartcon 246 f6h r/w a/d converter control register adcon 247 f7h r/w a/d converter data register (high byte) addatah 248 f8h r a/d converter data register (low byte) addatal 249 f9h r port 2 pull-up enable control register p2pur 250 fah r/w location fbh is not mapped location fch is factory use only basic timer counter register btcnt 253 fdh r location feh is not mapped interrupt priority register ipr 255 ffh r/w
S3C84H5/f84h5 control register 4-3 table 4-3. set 1, bank 1 registers register name mnemonic decimal hex r/w timer a, timer 1 interrupt pending register tintpnd 224 e0h r/w timer a control register tacon 225 e1h r/w timer a data register tadata 226 e2h r/w timer a counter register tacnt 227 e3h r timer 1(0) data register (high byte) t1datah0 228 e4h r/w timer 1(0) data register (low byte) t1datal0 229 e5h r/w timer 1(1) data register (high byte) t1datah1 230 e6h r/w timer 1(1) data register (low byte) t1datal1 231 e7h r/w timer 1(0) control register t1con0 232 e8h r/w timer 1(1) control register t1con1 233 e9h r/w timer 1(0) counter register (high byte) t1cnth0 234 eah r timer 1(0) counter register (low byte) t1cntl0 235 ebh r timer 1(1) counter register (high byte) t1cnth1 236 ech r timer 1(1) counter register (low byte) t1cntl1 237 edh r uart baud rate data register (high byte) brdatah 238 eeh r/w uart baud rate data register (low byte) brdatal 239 efh r/w sio pre-scalar register siops 240 f0h r/w sio data register siodata 241 f1h r/w serial i/o control register siocon 242 f2h r/w pwm data register (high) pwmdatah 243 f3h r/w pwm data register (low) pwmdatal 244 f4h r/w pwm control register pwmcon 245 f5h r/w location f6, f7h is not mapped watch timer control register wtcon 248 f8h r/w location f9h?ffh are not mapped
control registers S3C84H5/f84h5 4-4 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x r/w register addressing mode only .4 .3 .2 bit number: msb = bit 7 lsb = bit 0 .1 .0 x r/w x r/w x r/w x r/w x r/w 0 r 0 r/w figure 4-1. register description format
S3C84H5/f84h5 control register 4-5 adcon ? a/d converter control register f7h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? r/w r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 not used for the S3C84H5/f84h5(must keep always 0) .6?.4 a/d input pi n selection bits 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 adc6 1 1 1 adc7 .3 end-of-conversion bit (read-only) 0 a/d conversion opration is in progress 1 a/d conversion opration is complete .2?.1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 not used .0 start or enable bit 0 disable operation 1 start operation
control registers S3C84H5/f84h5 4-6 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 watchdog timer function disable code (for system reset) 1 0 1 0 disable watchdog timer function other vaules enable watchdog timer function .3?.2 basic timer input clock selection bits 0 0 fxx/4096 (3) 0 1 fxx/1024 1 0 fxx/128 1 1 fxx/1 (not used) .1 basic timer count er clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider cl ear bit for basic timer (2) 0 no effect 1 clear both clock frequency dividers notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to "00h". immediately following the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to "00h". immediately following the write operation, the btcon.0 value is automatically cleared to "0". 3. the fxx is selected clock for system (main osc. or sub osc.).
S3C84H5/f84h5 control register 4-7 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w ? ? ? addressing mode register addressing mode only .7?.5 not used for the S3C84H5/f84h5(must keep always 0) .4?.3 cpu clock (system clock) selection bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx/1 (non-divided) .2?.0 not used for the S3C84H5/f84h5(must keep always 0) note: after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4.
control registers S3C84H5/f84h5 4-8 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or underflow condition 1 operation generates a carry-out or underflow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no underflow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated underflow into bit 3 .1 fast interrupt status flag (fis) 0 interrupt return (iret) in progress (when read) 1 fast interrupt service routine in progress (when read) .0 bank address se lection flag (ba) 0 bank 0 is selected 1 bank 1 is selected
S3C84H5/f84h5 control register 4-9 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt level 7 (irq7) enable bit 0 disable (mask) 1 enable (un-mask) .6 interrupt level 6 (irq6) enable bit 0 disable (mask) 1 enable (un-mask) .5 interrupt level 5 (irq5) enable bit 0 disable (mask) 1 enable (un-mask) .4 interrupt level 4 (irq4) enable bit 0 disable (mask) 1 enable (un-mask) .3 interrupt level 3 (irq3) enable bit 0 disable (mask) 1 enable (un-mask) .2 interrupt level 2 (irq2) enable bit 0 disable (mask) 1 enable (un-mask) .1 interrupt level 1 (irq1) enable bit 0 disable (mask) 1 enable (un-mask) .0 interrupt level 0 (irq0) enable bit 0 disable (mask) 1 enable (un-mask) note: when an interrupt level is masked, any interrupt requests that may be issued are not recognized by the cpu.
control registers S3C84H5/f84h5 4-10 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah).
S3C84H5/f84h5 control register 4-11 ipr ? interrupt priority regi ster ffh set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 interrupt group c priority control bit 0 irq5 > (irq6, irq7) 1 (irq6, irq7) > irq5 .3 interrupt subgroup b pr iority control bit 0 irq3 > irq4 1 irq4 > irq3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 (irq3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0
control registers S3C84H5/f84h5 4-12 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only .7 interrupt level 7 (i rq7) request pending bit 0 not pending 1 pending .6 interrupt level 6 (i rq6) request pending bit 0 not pending 1 pending .5 interrupt level 5 (i rq5) request pending bit 0 not pending 1 pending .4 interrupt level 4 (i rq4) request pending bit 0 not pending 1 pending .3 interrupt level 3 (i rq3) request pending bit 0 not pending 1 pending .2 interrupt level 2 (i rq2) request pending bit 0 not pending 1 pending .1 interrupt level 1 (i rq1) request pending bit 0 not pending 1 pending .0 interrupt level 0 (i rq0) request pending bit 0 not pending 1 pending
S3C84H5/f84h5 control register 4-13 osccon ? oscillator control regist er f2h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w r/w ? r/w addressing mode register addressing mode only .7?.4 not used for the s3c84i8/f84i9 (must keep always 0) .3 main system oscillator control bit 0 main system oscillator run 1 main system oscillator stop .2 sub system oscillator control bit 0 sub system oscillator run 1 sub system oscillator stop .1 not used for the S3C84H5/f84h5 (must keep always 0) .0 system clock selection bit 0 main oscillator select 1 subsystem oscillator select
control registers S3C84H5/f84h5 4-14 p0con ? port 0 control register (h igh byte) e6h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p0.3/ad3 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 alternative function mode; ad3 input .5?.4 p0.2/ad2 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 alternative function mode; ad2 input .3?.2 p0.1/ ad1 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 alternative function mode; ad1 input .1?.0 p0.0/ ad0 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 alternative function mode; ad0 input note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
S3C84H5/f84h5 control register 4-15 p1conh ? port 1 control register (high byte) e8h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for the S3C84H5/f84h5 (must keep always 0) .3?.2 p1.5/t1cap1/ad6 configration bits 0 0 input mode (t1cap1 input) 0 1 input mode with pull-up (t1cap1 input) 1 0 push-pull output mode 1 1 alternative function mode: ad6 .1?.0 p1.4/t1ck1/ad5 configration bits 0 0 input mode; (t1ck1 input) 0 1 input mode with pull-up; (t1ck1 input) 1 0 push-pull output mode 1 1 alternative function mode: ad5 note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
control registers S3C84H5/f84h5 4-16 p1conl ? port 1 control register (low byte) e9h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p1.3/t1out0/int3 configration bits 0 0 input mode ; interrupt input (int3) 0 1 input mode with pull-up ; interrupt input (int3) 1 0 push-pull output mode 1 1 alternative function mode: t1out0 mode .5?.4 p1.2/tacap/int2 configration bits 0 0 input mode ; interrupt input (int2); tacap 0 1 input mode with pull-up ; interrupt input (int2) ; tacap 1 0 push-pull output mode 1 1 alternative function mode: not used .3?.2 p1.1/tack/buz/int1 configration bits 0 0 input mode ; interrupt input (int1); tack 0 1 input mode with pull-up ; interrupt input (int1); tack 1 0 push-pull output mode 1 1 alternative function mode: buz out mode .1?.0 p1.0/taout/int0 configration bits 0 0 input mode ; interrupt input (int0) 0 1 input mode with pull-up ; interrupt input (int0) 1 0 push-pull output mode 1 1 alternative function mode: taout mode note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
S3C84H5/f84h5 control register 4-17 p1intpnd ? port 1 interrupt pending register eah set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for S3C84H5/f84h5 .3 p1.3/int3 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .2 p1.2/int2 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .1 p1.1/int1 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .0 p1.0/int0 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending
control registers S3C84H5/f84h5 4-18 p1int ? port 1 interrupt enable ebh set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p1.3's interrupt enable/disble selection bit 0 x interrupt disable 1 0 interrupt enab le; falling edge 1 1 interrupt enable; rising edge .5?.4 p1.2's interrupt enable/disble selection bit 0 x interrupt disable 1 0 interrupt enab le; falling edge 1 1 interrupt enable; rising edge .3?.3 p1.1's interrupt enable/disble selection bit 0 x interrupt disable 1 0 interrupt enab le; falling edge 1 1 interrupt enable; rising edge .1?.0 p1.0's interrupt enable/disble selection bit 0 x interrupt disable 1 0 interrupt enab le; falling edge 1 1 interrupt enable; rising edge
S3C84H5/f84h5 control register 4-19 p2conh ? port 2 control register (high byte) ech set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p2.7/txd configration bits 0 0 input mode 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: txd output .5?.4 p2.6/rxd configration bits 0 0 input mode ; rxd input 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: rxd output .3?.2 p2.5/sck configration bits 0 0 input mode ; sck input 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: sck output .1?.0 p2.4/so configration bits 0 0 input mode 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: so output note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
control registers S3C84H5/f84h5 4-20 p2conl ? port 2 control register (low byte) edh set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p2.3/ad7/si configration bits 0 0 input mode ;si input 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: ad7 .5?.4 p2.2/ad4/t1out1 configration bits 0 0 input mode ; 0 1 alternative function mode: t1out1 1 0 push-pull output mode 1 1 alternative function mode: ad4 .3?.2 p2.1/pwm/t1cap0 configration bits 0 0 input mode ;t1cap0 input 0 1 alternative function mode: not used 1 0 push-pull output mode 1 1 alternative function mode: pwm mode .1?.0 p2.0/tbpwm/t1ck0 configration bits 0 0 input mode ; t1ck0 input 0 1 alternative function mode: t1ck0 input 1 0 push-pull output mode 1 1 alternative function mode: tbpwm mode note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
S3C84H5/f84h5 control register 4-21 p2pur ? port 2 pull-up resistor cont rol register fah set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 p2.7 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .6 p2.6 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .5 p2.5 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .4 p1.4 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .3 p2.3 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .2 p2.2 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .1 p2.1 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable .0 p2.0 pull-up resistor enable/disable 0 pull-up resistor disable 1 pull-up resistor enable
control registers S3C84H5/f84h5 4-22 p3conl ? port 3 control register (low byte) efh set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p3.3 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 n-channel open-drain output .5?.4 p3.2 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 n-channel open-drain output .3?.3 p3.1 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 n-channel open-drain output .1?.0 p3.0 configration bits 0 0 input mode 0 1 input mode with pull-up 1 0 push-pull output mode 1 1 n-channel open-drain output note: in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
S3C84H5/f84h5 control register 4-23 pp ? register page pointer dfh set1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.4 destination register page selection bits 0 0 0 0 destination: page 0 other values don?t care .3-.0 source register page selection bits 0 0 0 0 source: page 0 other values don?t care note: in the S3C84H5/f84h5 microcontroller, the internal register file is configured as one page (pages 0). the pages 0 are used for the general-purpose register file and data register.
control registers S3C84H5/f84h5 4-24 pwmcon ? pwm control register f5h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 ? 0 0 0 0 0 read/write r/w r/w ? r/w r/w r/w r/w r/w .7?.6 pwm input cloc k selection bits 0 0 f osc /64 0 1 f osc /8 1 0 f osc /2 1 1 f osc /1 .5 not used for S3C84H5/f84h5 .4 pwmdata reload interval selection bit 0 reload from 10-bit up counter overflow 1 reload from 8-bit up counter overflow .3 pwm counter clear bit 0 no effect 1 clear the pwm counter (when write) .2 pwm counter enable bit 0 stop counter 1 start (resume countering) .1 pwm overflow interrupt enable bit (8-bit overflow) 0 disable interrupt 1 enable interrupt .0 pwm overflow interrupt pending bit 0 no interrupt pending (when read) 0 clear pending bit (when write) 1 interrupt is pending (when read) note: pwmcon.3 is not auto-cleared. you must pay attention when clear pending bit. (refer to page 13-7).
S3C84H5/f84h5 control register 4-25 rp0 ? register pointer 0 d6h set1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7-.3 register pointer 0 address value register pointer 0 can independently point to one of the 256-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h?c7h. .2-.0 not used for the S3C84H5/f84h5 rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7-.3 register pointer 1 address value register pointer 1 can independently point to one of the 256-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2-.0 not used for the S3C84H5/f84h5
control registers S3C84H5/f84h5 4-26 siocon ? serial i/o module control registers f2h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7 sio shift cloc k selection bit 0 interval clock (p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb-first mode 1 lsb-first mode .5 sio mode selection bit 0 receive-only mode 1 transmit/receive mode .4 shift clock e dge selection bit 0 tx at falling edges, rx at rising edges. 1 tx at rising edges, rx at falling edges. .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting .2 sio shift operation enable bit 0 disable shift and clock counter 1 enable shift and clock counter .1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt .0 sio interrupt pending bit 0 no interrupt pending 1 interrupt pending ( clear pending bit when write)
S3C84H5/f84h5 control register 4-27 siops ? sio prescaler register f0h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 baud rate = input clock (fxx)/[(siops + 1) 4] or sck input clock sph ? stack pointer (high byte) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in register spl (d9h). the sp value is undefined following a reset. spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in register sph (d8h). the sp value is undefined following a reset.
control registers S3C84H5/f84h5 4-28 stopcon ? stop control register e5h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stop control bits 1 0 1 0 0 1 0 1 enable stop instruction other values disable stop instruction note: before execute the stop instruction, you must set this stpcon register as ?10100101b?. otherwise the stop instruction will not be executed.
S3C84H5/f84h5 control register 4-29 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 x x x 0 0 read/write ? ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.5 not used, but you must keep always 0 .4?.2 fast interrupt le vel selection bits 0 0 0 irq0 0 0 1 irq1 0 1 0 irg2 0 1 1 irq3 1 0 0 irq4 1 0 1 irq5 1 1 0 irq6 1 1 1 irq7 .1 fast interrupt enable bit 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit (note) 0 disable global interrupt processing 1 enable global interrupt processing note: following a reset, you enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0).
control registers s3f84i5/f84i9 4-30 t1con0 ? timer 1(0) control register e8h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.5 timer 1(0) input clock selection bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx 1 0 1 external clock falling edge 1 1 0 external clock rising edge 1 1 1 counter stop .4?.3 timer 1(0) operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, ovf can occur) 1 0 capture mode (capture on falling edge, ovf can occur) 1 1 pwm mode .2 timer 1(0) counter enable bit 0 no effect 1 clear the timer 1(0) counter (auto-clear bit) .1 timer 1(0) match/capt ure interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1(0) overflow interrupt enable 0 disable overflow interrupt 1 enable overflow interrupt
s3f84i5/f84i9 control register 4-31 t1con1 ? timer 1(1) control register e9h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.5 timer 1(1) input clock selection bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx 1 0 1 external clock falling edge 1 1 0 external clock rising edge 1 1 1 counter stop .4-.3 timer 1(1) operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, ovf can occur) 1 0 capture mode (capture on falling edge, ovf can occur) 1 1 pwm mode .2 timer 1(1) c ounter enable bit 0 no effect 1 clear the timer 1(1) counter (auto-clear bit) .1 timer 1(1) match/capt ure interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1(1) overflow interrupt enable 0 disable overflow interrupt 1 enable overflow interrupt
control registers s3f84i5/f84i9 4-32 tacon ? timer a control regist er e1h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 timer a input cl ock selection bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 external clock (tack) .5-.4 timer a operating mode selection bits 0 0 interval mode (taout mode) 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counte r running, ov f can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer a count er clear bit 0 no effect 1 clear the timer a counter (auto-clear bit) .2 timer a overflow interrupt enable bit 0 disable overflow interrupt 1 enable overflow interrupt .1 timer a match/captur e interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer a st art/stop bit 0 stop timer a 1 start timer a
s3f84i5/f84i9 control register 4-33 tbcon ? timer b control register d0h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer b input cl ock selection bits 0 0 fxx/4 0 1 fxx/8 1 0 fxx/64 1 1 fxx/256 .5?.4 timer b interrupt time selection bits 0 0 elapsed time for low data value 0 1 elapsed time for high data value 1 0 elapsed time for low and high data values 1 1 not used .3 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt .2 timer b st art/stop bit 0 stop timer b 1 start timer b .1 timer b mode selection bit 0 one-shot mode 1 repeating mode .0 timer b output fl ip-flop control bit 0 t-ff is low 1 t-ff is high note: fxx is selected clock for system.
control registers S3C84H5/f84h5 4-34 tintpnd ? timer a, timer 1 interrupt pe nding register e0h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset v alue 0 0 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 not used for the S3C84H5/f84h5 (must keep always 0) .5 timer 1(1) overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .4 timer 1(1) match/capt ure interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .3 timer 1(0) overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .2 timer 1(0) match/capt ure interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .1 timer a overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .0 timer a match/captur e interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending
S3C84H5/f84h5 control register 4-35 uartcon ? uart control register f6h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .7?.6 operating mode and baud rate selection bits 0 0 mode 0: shift register [fxx/(16 (16bit brdata + 1))] 0 1 mode 1: 8-bit uart [fxx/(16 (16bit brdata + 1))] 1 x mode 2: 9-bit uart [fxx/(16 (16bit brdata + 1))] .5 multiprocessor communication (1) enable bit (for mode 2 only) 0 disable 1 enable .4 serial data re ceive enable bit 0 disable 1 enable .3 if parity disable mode (pen = 0), location of the 9 th data bit to be transmitted in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for transmit data in uart mode 2. 0 : even parity bit generation for transmit data 1 : odd parity bit generation for transmit data .2 if parity disable (pen = 0), location of the 9 th data bit that was received in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for receive data in uart mode 2. 0 : even parity check for the received data 1 : odd parity check for the received data a result of parity error will be saved in rpe bit of the uartpnd register after parity checking of the received data.
control registers S3C84H5/f84h5 4-36 uartcon ? uart control register (continued) f6h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w .1 receive interrupt enable bit 0 disable receive interrupt 1 enable receive interrupt .0 transmit interrupt enable bit 0 disable transmit interrupt 1 enable transmit interrupt notes: 1. in mode 2, if the mce (uartcon.5) bit is set to "1", then the receive interrupt will not be activated if the received 9 th data bit is "0". in mode 1, if mce = "1?, then the receive interrupt will not be activated if a valid stop bit was not received. in mode 0, the mce (uartcon.5) bit should be "0". 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits for serial data receive and transmit. 3. parity enable bits, pen, are located in the uartpnd register at address f4h, bank 0. 4. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only.
S3C84H5/f84h5 control register 4-37 uartpnd ? uart pending and parity control f4h set1, bank0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? ? r/w r/w ? ? r/w r/w .7-.6 not used for the s3f84i5/f84i9(must keep always 0) .5 uart parity enable/disable (pen) 0 disable 1 enable .4 uart receive parity error (rpe) 0 no error 1 parity error .3-.2 not used for the s3f84i5/f84i9(must keep always 0) .1 uart receive interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending .0 uart transmit interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. to avoid programming errors, we recommend using load instruction (except for ldb), when manipulating uartpnd values. 3. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. 4. parity error bit (rpe) will be refreshed whenever 8th receive data bit has been shifted.
control registers S3C84H5/f84h5 4-38 wtcon ? watch timer control regi ster f8h set1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 watch timer cl ock selection bit 0 main system clock divided by 256 (fxx/256) 1 sub system clock (fxt) .6 watch timer interrupt enable bit 0 disable watch timer interrupt 1 enable watch timer interrupt .5?.4 buzzer signal selection bits 0 0 0.5 khz buzzer (bzout) signal output 0 1 1 khz buzzer (bzout) signal output 1 0 2 khz buzzer (bzout) signal output 1 1 4 khz buzzer (bzout) signal output .3?.2 watch timer sp eed selection bits 0 0 0.5 s interval 0 1 0.25 s interval 1 0 0.125 s interval 1 1 1.955 ms interval .1 watch timer enable bit 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer .0 watch timer in terrupt pending bit 0 interrupt is not pending 1 clear pending bit when write 1 interrupt is pending
S3C84H5/f84h5 in terrupt structure 5-1 5 interrupt structure overview the s3c8-series interrupt structure has three basic components: levels, vectors, and sources. the sam8 cpu recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. a vector address can be assigned to one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight possible interrupt levels: irq0?irq7, also called level 0?level 7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. the S3C84H5/f84h5 interrupt structure recognizes eight interrupt levels. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are just identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128 (the actual number of vectors used for s3c8-series devices is always much smaller). if an interrupt level has more than one vector address, the vector priorities are set in hardware. S3C84H5/f84h5 uses sixteen vectors. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow. each vector can have several interrupt sources. in the S3C84H5/f84h5 interrupt structure, there are sixteen possible interrupt sources. when a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit.
interrupt structure S3C84H5/f84h5 5-2 interrupt types the three components of the s3c8 interrupt structure described before ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level (irq n) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the S3C84H5/f84h5microcontroller, two interrupt types are implemented. v ectors sources levels s1 v1 s2 type 2: irqn s3 sn v1 s1 v2 s2 type 3: irqn v3 s3 v1 s1 type 1: irqn vn s n+ 1 sn sn + 2 sn + m not es: 1. the number of sn and vn value is expandable 2. in the S3C84H5/f84h5 implementation, interrupt types 1 and 3 are used. figure 5-1. s3c8-ser ies interrupt types
S3C84H5/f84h5 in terrupt structure 5-3 S3C84H5/f84h5 interrupt structure the S3C84H5/f84h5 microcontroller supports sixteen interrupt sources. all of the interrupt sources have a corresponding interrupt vector address. eight interrupt levels are recognized by the cpu in this device-specific interrupt structure, as shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (the relative priorities of multiple interrupts within a single level are fixed in hardware). when the cpu grants an interrupt request, interrupt processing starts. all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed.
interrupt structure S3C84H5/f84h5 5-4 vectors sources levels reset(clear) timer a match/capture irq1 timer a overflow h/w, s/w h/w, s/w c0h c2h c4h c6h c8h cah irq2 timer 1(0) match/capture timer 1(0) overflow timer 1(1) match/capture timer 1(1) overflow h/w, s/w h/w, s/w h/w, s/w h/w, s/w timer b underflow beh irq0 h/w irq3 ceh d0h d2h d4h irq4 p1.0 external interrupt p1.1 external interrupt p1.2 external interrupt p1.3 external interrupt s/w s/w s/w s/w d6h irq5 watch timer s/w d8h dah irq6 sio receive/transmit pwm overflow interrupt s/w s/w dch deh irq7 uart data receive uart data transmit s/w s/w notes: 1. within a given interrupt level, the lower vector address has high priority. for example, dch has higher priority than deh within the level irq5 the priorities within each le vel are set at the factory. 2. external interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. figure 5-2. S3C84H5/f84h5interrupt structure
S3C84H5/f84h5 interrupt structure 5-5 interrupt vector addresses all interrupt vector addresses for the S3C84H5/f84h5 interrupt structure are stored in the vector address area of the internal 16-kbyte rom, 0h?3fffh (see figure 5-3). you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses (table 5-1 lists all vector addresses). the program reset address in the rom is 0100h. 16,383 0 255 00h 0100h ffh 3fffh (h e x ) reset address i n te rru p t vector address area 16-kbyte figure 5-3. rom vect or address area
interrupt structure S3C84H5/f84h5 5-6 table 5-1. interrupt vectors vector address re quest reset/clear decimal value hex value interrupt source interrupt level priority in level h/w s/w 256 100h basic timer (wdt) overflow nreset ? 222 deh uart transmit irq7 1 220 dch uart receive 0 218 dah pwm overflow interrupt irq6 ? 216 d8h sio receive / transmit irq5 ? 214 d6h watch timer interrupt irq4 ? 212 d4h p1.3 external interrupt irq3 3 210 d2h p1.2 external interrupt 2 208 d0h p1.1external interrupt 1 206 ceh p1.0 external interrupt 0 202 cah timer 1(1) overflow irq2 3 200 c8h timer 1(1) match/capture 2 198 c6h timer 1(0) overflow 1 196 c4h timer 1(0) match/capture 0 194 c2h timer a overflow irq1 1 192 c0h timer a match/capture 0 190 beh timer b underflow irq0 ? notes: 1. interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. the priorities within a given level are fixed in hardware.
S3C84H5/f84h5 interrupt structure 5-7 enable/disable interrupt instructions (ei, di) executing the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are then serviced as they occur according to the established priorities. note the system initialization routine executed after a reset must always contain an ei instruction to globally enable the interrupt structure. during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables (un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative priorities of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing (sym settings also enable fast interrupts and control the activity of external interface, if implemented). table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the eight interrupt levels: irq0?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the seven levels of s3f84i5/f84i9are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2, irq3 and irq4, and group c is irq5, irq6, and irq7. interrupt request register irq r this register contains a request pending bit for each interrupt level. system mode register sym r/w this register enables/disables fast interrupt processing, dynamic global interrupt processing. note: before imr register is changed to any value, all interrupts must be disable. using di instruction is recommended.
interrupt structure S3C84H5/f84h5 5-8 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. the system-level control points in the interrupt structure are: ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0) ? interrupt level enable/disab le settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corresponding peripheral control registers note when writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. interrupt request register (read-only) irq0-irq7 interrupts interrupt mask register polling cycle interrupt priority register global interrupt control (ei, di or sym.0 manipulation) s r q reset ei vector interrupt cycle figure 5-4. interrupt function diagram
S3C84H5/f84h5 interrupt structure 5-9 peripheral interrupt control registers for each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see table 5-3). table 5-3. interrupt source control and data registers interrupt source interr upt level register(s) location(s) in set1 timer b underflow irq0 tbcon d0h tbdatah, tbdatal d1h, d2h, timer a overflow irq1 tintpnd e0h, bank 1 timer a match/capture tacon e1h, bank 1 tadata e2h, bank 1 tacnt e3h, bank 1 timer 1(0) match/capture irq2 t1datah0,t1datal0 e4h, e5h, bank 1 timer 1(0) overflow t1datah1,t1datal1 e6h, e7h, bank 1 timer 1(1) match/capture t1con0, t1con1 e8h, e9h, bank 1 timer 1(1) overflow t1cnth0, t1cntl0 eah, ebh, bank 1 t1cnth1, t1cntl1 ech, edh, bank 1 tintpnd e0h, bank 1 p1.0 external interrupt irq3 p1conl e9h, bank 0 p1.1 external interrupt p1int ebh, bank 0 p1.2 external interrupt p1intpnd eah, bank 0 p1.3 external interrupt f3h, bank 0 watch timer interrupt irq4 wtcon f8h, bank 1 sio receive/transmit irq5 siocon,siodata f1h,f2h bank 1 pwm overflow irq6 pwmcon f5h, bank 1 pwmdatah,pwmdatal f3h,f4h bank 1 uart receive/transmit irq7 uartcon f6h, bank 0 udata, uartpnd f5h, f4h, bank 0 brdatah, brdatal eeh, efh, bank 1
interrupt structure S3C84H5/f84h5 5-10 system mode register (sym) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing (see figure 5-5). a reset clears sym.0 to "0". the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. in order to enable interrupt processing an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb global interrupt enable bit: 0 = disable all interrupts processing 1 = enable all interrupts processing fast interrupt enable bit: 0 = disable fast interrupts processing 1 = enable fast interrupts processing fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 not used for the S3C84H5/f84h5 figure 5-5. system mode register (sym)
S3C84H5/f84h5 interrupt structure 5-11 interrupt mask register (imr) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 irq0 interrupt level # enable bit 0 = disable irq# interrupt 1 = enable irq# interrupt irq1 irq2 irq3 irq4 irq5 irq6 irq7 figure 5-6. interrupt mask register (imr)
interrupt structure S3C84H5/f84h5 5-12 interrupt priority register (ipr) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt sources are active, the source with the highest priority level is serviced first. if two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (this priority is fixed in hardware). to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq2, irq3, irq4 group c irq5, irq6, irq7 ipr group b irq2 b1 irq4 b2 irq3 b22 b21 ipr group a irq1 a2 irq0 a1 ipr group c c1 irq7 c2 irq6 c22 c21 irq5 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting "001b" for these bits would select the group relationship b > c > a. the setting "101b" would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group c includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. ipr.6 defines the subgroup c relationship. ipr.5 controls the interrupt group c. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts.
S3C84H5/f84h5 interrupt structure 5-13 group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 interrupt priority register (ipr) ffh ,set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 group priority: 0 0 0 = undefined 0 0 1 = b > c > a 0 1 0 = a > b >c 0 1 1 = b > a > c 1 0 0 = c > a > b 1 0 1 = c > b > a 1 1 0 = a > c > b 1 1 1 = undefined d7 d4 d1 figure 5-8. interrupt pr iority register (ipr)
interrupt structure S3C84H5/f84h5 5-14 interrupt request register (irq) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller?s interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level. a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to ?0?. you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch ,set 1, r lsb msb .7 .6 .5 .4 .3 .2 .1 .0 irq0 interrupt level # request pending bit 0 = irq# interrupt is not pending 1 = irq# interrupt is pending irq1 irq2 irq3 irq4 irq5 irq6 irq7 figure 5-9. interrupt re quest register (irq)
S3C84H5/f84h5 interrupt structure 5-15 interrupt pending function types overview there are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. pending bits cleared auto matically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source by sending an iack, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the S3C84H5/f84h5 interrupt structure, the timer b underflow interrupt (irq0) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit is the one that should be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source?s mode or control register. in the S3C84H5/f84h5 interrupt structure, pending conditions for irq3, irq4, irq5, irq6, and irq7 must be cleared in the interrupt service routine.
interrupt structure S3C84H5/f84h5 5-16 interrupt source polling sequence the interrupt request po lling and servicin g sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedur e identifies a pending co ndition for that source. 3. the cpu checks the interrupt level of source. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues pollin g for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the interrupt level must have the highest priority if more than one level is currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) when all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags, setting sym.0 to "1". it a llows the cpu to process the next interrupt request.
S3C84H5/f84h5 interrupt structure 5-17 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine specified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range of 00h?ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher priority interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the procedure above to some extent.
S3C84H5/f84h5 instruction set 6-1 6 instruction set overview the instruction set is specifically designed to support large register files that are typical of most s3c8-series microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0?255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data, 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to chapter 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to chapter 3, "addressing modes."
instruction set S3C84H5/f84h5 6-2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldb dst,src load bit lde dst,src load external data memory ldc dst,src load program memory lded dst,src load external data memory and decrement ldcd dst,src load program memory and decrement ldei dst,src load external data memory and increment ldci dst,src load program memory and increment ldepd dst,src load external data memory with pre-decrement ldcpd dst,src load program memory with pre-decrement ldepi dst,src load external data memory with pre-increment ldcpi dst,src load program memory with pre-increment ldw dst,src load word pop dst pop from stack popud dst,src pop user stack (decrementing) popui dst,src pop user stack (incrementing) push src push to stack pushud dst,src push user stack (decrementing) pushui dst,src push user stack (incrementing) note: lde, lded, ldei, ldepp, and ldepi instructions can be used to read/write the data from the 64-kbyte data memory.
S3C84H5/f84h5 instruction set 6-3 table 6-1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,sr c multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or
instruction set S3C84H5/f84h5 6-4 table 6-1. instruction gr oup summary (continued) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask
S3C84H5/f84h5 instruction set 6-5 table 6-1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode
instruction set S3C84H5/f84h5 6-6 flags register (flags) the flags register flags contains eight bits which describ e the current status of cpu operations. four of these bits, flags.7?flags.4, can be tested and used with conditional jump instructions. two other flag bits, flags.3 and flags.2, are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether register bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and inst ruction uses the flags register as the destination, th en two write will simultaneously occur to the flags register producing an unpredictable result. system flags register (flags) d5h ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 bank address status flag (ba) fast interrupt status flag (fs) half-carry flag (h) decimal adjust flag (d) carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6-1. system fl ags register (flags)
S3C84H5/f84h5 instruction set 6-7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operatio ns have been performed, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. in operations that test register bits, and in shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations , the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is cleared to "0" after a logic operation has been performed. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and it cannot be addressed as a test condition. h half-carry flag (flags.2 ) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is normally not accessed directly by a program. fis fast interrupt stat us flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when the sb0 instruction is executed and is set to "1" (select bank 1) when the sb1 instruction is executed.
instruction set S3C84H5/f84h5 6-8 instruction set notation table 6-2. flag no tation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruct ion pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode
S3C84H5/f84h5 instruction set 6-9 table 6-4. instructi on notation conventions notation description ac tual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit "b" of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg[rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr[rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = a number from +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = 0?65535)
instruction set S3C84H5/f84h5 6-10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs
S3C84H5/f84h5 instruction set 6-11 table 6-5. opcode quic k reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop
instruction set S3C84H5/f84h5 6-12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic desc ription flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicate condition codes which are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used. following a cp instruction, you would probably want to use the instruction eq. 2. for operations using unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used.
S3C84H5/f84h5 instruction set 6-13 instruction descriptions this chapter contains detailed information and programming examples for each instruction in the s3c8-series instruction set. information is arranged in a consistent format for improved readability and for quick reference. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? flag settings that may be affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction
instruction set S3C84H5/f84h5 6-14 adc ? add with carry adc dst,src operation: dst dst + src + c the source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. in multiple-precision arithm etic, this instruct ion lets the carr y value from the addition of low-order operands be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most signific ant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 r1 = 14h, r2 = 03h adc r1,@r2 r1 = 1bh, r2 = 03h adc 01h,02h register 01h = 24h, register 02h = 03h adc 01h,@02h register 01h = 2bh, register 02h = 03h adc 01h,#11h register 01h = 32h in the first example, the destination register r1 contains the value 10h, the carry flag is set to "1" and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in the register r1.
S3C84H5/f84h5 instruction set 6-15 add ? add add dst,src operation: dst dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 r1 = 15h, r2 = 03h add r1,@r2 r1 = 1ch, r2 = 03h add 01h,02h register 01h = 24h, register 02h = 03h add 01h,@02h register 01h = 2bh, register 02h = 03h add 01h,#25h register 01h = 46h in the first example, the destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in the register r1.
instruction set S3C84H5/f84h5 6-16 and ? logical and and dst,src operation: dst dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 r1 = 02h, r2 = 03h and r1,@r2 r1 = 02h, r2 = 03h and 01h,02h register 01h = 01h, register 02h = 03h and 01h,@02h register 01h = 00h, register 02h = 03h and 01h,#25h register 01h = 21h in the first example, the destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in the register r1.
S3C84H5/f84h5 instruction set 6-17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) dst(0) and src(b) or dst(b) dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or the source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note: in the second byte of the 3-byte instruction formats, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1,01h.1 r1 = 06h, register 01h = 05h band 01h.1,r1 register 01h = 05h, r1 = 07h in the first example, the source register 01h contains the value 05h (00000101b) and the destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of the register r1 (destination), leaving the value 06h (00000110b) in the register r1.
instruction set S3C84H5/f84h5 6-18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address "0" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 r1 = 07h, register 01h = 01h if the destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h).
S3C84H5/f84h5 instruction set 6-19 bitc ? bit complement bitc dst.b operation: dst(b) not dst(b) this instruction complements the specified bit with in the destination without affecting any other bit in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 r1 = 05h if the working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in the register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared.
instruction set S3C84H5/f84h5 6-20 bitr ? bit reset bitr dst.b operation: dst(b) 0 the bitr instruction clears the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address ?0? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 r1 = 05h if the value of the working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b).
S3C84H5/f84h5 instruction set 6-21 bits ? bit set bits dst.b operation: dst(b) 1 the bits instruction sets the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note: in the second byte of the instruction format, the destination address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 r1 = 0fh if the working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b).
instruction set S3C84H5/f84h5 6-22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) dst(0) or src(b) or dst(b) dst(b) or src(0) the specified bit of the source (or the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 r1 = 07h, register 01h = 03h bor 01h.2, r1 register 01h = 07h, r1 = 07h in the first example, the destination working register r1 contains the value 07h (00000111b) and the source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of the register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in the working register r1. in the second example, the destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of the register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in the register 01h.
S3C84H5/f84h5 instruction set 6-23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter. otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip,r1.3 pc jumps to skip location if the working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip (remember that the memory location must be within the allowed range of + 127 to ? 128).
instruction set S3C84H5/f84h5 6-24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc. otherwise, the inst ruction following the btjrt instruction is executed. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip,r1.1 if the working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the me mory location pointed to by the skip. remember that the memory location addressed by the btjrt instruction must be within the allowed range of + 127 to ? 128.
S3C84H5/f84h5 instruction set 6-25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) dst(0) xor src(b) or dst(b) dst(b) xor src(0) the specified bit of the source (or the destination) is logically exclusive-ored with bit zero (lsb) of the destination (or the source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefinsed. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 01h = 03h (00000011b): bxor r1,01h.1 r1 = 06h, register 01h = 03h bxor 01h.2,r1 register 01h = 07h, r1 = 07h in the first example, the destination working register r1 has the value 07h (00000111b) and the source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive-ors bit one of the register 01h (the source) with bit zero of r1 (the destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of the source register 01h is unaffected.
instruction set S3C84H5/f84h5 6-26 call ? call procedure call dst operation: sp sp?1 @sp pcl sp sp?1 @sp pch pc dst the contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where, 4ah is the address that follows the instruction.) call @rr0 sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to the memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and the stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and the stack pointer are the same as in the first example, if the program address 0040h contains 35h and the program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example.
S3C84H5/f84h5 instruction set 6-27 ccf ? complement carry flag ccf operation: c not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero. if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one.
instruction set S3C84H5/f84h5 6-28 clr ? clear clr dst operation: dst "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h register 00h = 00h clr @01h register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h.
S3C84H5/f84h5 instruction set 6-29 com ? complement com dst operation: dst not dst the contents of the destination location are complemented (one's complement). all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 r1 = 0f8h com @r1 r1 = 07h, register 07h = 0eh in the first example, the destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and logic zeros to logic ones, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of the destination register 07h (11110001b), leaving the new value 0eh (00001110b).
instruction set S3C84H5/f84h5 6-30 cp ? compare cp dst,src operation: dst?src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 set the c and s flags the destination working register r1 contains the value 02h and the source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, the c and the s flag values are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, the destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in the working register r3.
S3C84H5/f84h5 instruction set 6-31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst?src = "0", pc pc + ra ir ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 c2 r ir example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1,@r2,skip r2 = 04h, pc jumps to skip location in this example, the working register r1 contains the value 02h, the working register r2 the value 03h, and the register 03 contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. remember that the memory location addressed by the cpije instruction must be within the allowed range of + 127 to ? 128.
instruction set S3C84H5/f84h5 6-32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst?src "0", pc pc + ra ir ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 d2 r ir example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip r2 = 04h, pc jumps to skip location the working register r1 contains the value 02h, the working register r2 (the source pointer) the value 03h, and the general register 03 the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non- equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. remember that the memory location addressed by the cpijne instruction must be within the allowed range of + 127 to ? 128.
S3C84H5/f84h5 instruction set 6-33 da ? decimal adjust da dst operation: dst da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed (the operation is undefined if the destination operand is not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir
instruction set S3C84H5/f84h5 6-34 da ? decimal adjust da (continued) example: given: the working register r0 contains the value 15 (bcd), the working register r1 contains 27 (bcd), and the address 27h contains 46 (bcd): add r1,r0 ; c "0", h "0", bits 4?7 = 3, bits 0?3 = c, r1 3ch da r1 ; r1 3ch + 06 if an addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using the standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c "0", h "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 31?0 leave the value 31 (bcd) in the address 27h (@r1).
S3C84H5/f84h5 instruction set 6-35 dec ? decrement dec dst operation: dst dst?1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 r1 = 02h dec @r1 register 03h = 0fh in the first example, if the working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh.
instruction set S3C84H5/f84h5 6-36 decw ? decrement word decw dst operation: dst dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 r0 = 12h, r1 = 33h decw @r2 register 30h = 0fh, register 31h = 20h in the first example, the destination register r0 contains the value 12h and the register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, it is recommended to use decw as shown in the following example. loop decw rr0 ld r2,r1 or r2,r0 jr nz,loop
S3C84H5/f84h5 instruction set 6-37 di ? disable interrupts di operation: sym (0) 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if the value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing.
instruction set S3C84H5/f84h5 6-38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) remainder dst (lower) quotient the destination operand (16 bits) is divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 28, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and the quotient is between 28 and 29 ?1; cleared otherwise. z: set if the divisor or the quotient = "0"; cleared otherwise. s: set if msb of the quotient = "1"; cleared otherwise. v: set if the quotient is 28 or if the divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 26/10 * 94 rr r 26/10 * 95 rr ir 26/10 * 96 rr im * execution takes 10 cycles if the divide-by-zero is attempted, otherwise, it takes 26 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 r0 = 03h, r1 = 40h div rr0,@r2 r0 = 03h, r1 = 20h div rr0,#20h r0 = 03h, r1 = 80h in the first example, the destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and the register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1).
S3C84H5/f84h5 instruction set 6-39 djnz ? decrement and jump if non-zero djnz r,dst operation: r r ? 1 if r 0, pc pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is + 127 to ? 128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0 or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1,loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, the working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements the register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label.
instruction set S3C84H5/f84h5 6-40 ei ? enable interrupts ei operation: sym (0) 1 the ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have the highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when the ei instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.)
S3C84H5/f84h5 instruction set 6-41 enter ? enter enter operation: sp sp ? 2 @sp ip ip pc pc @ip ip ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows an example of how to use an enter statement. ip data address data 40 41 42 43 address data 1f 01 10 memory stack 0050 before 0022 0040 pc 22 iph ipl data ip address data 40 41 42 43 address data 1f 01 10 memory stack enter address h address l address h 0043 0020 0110 pc enter address h address l address h routine 110 20 21 22 after 00 50
instruction set S3C84H5/f84h5 6-42 exit ? exit exit operation: ip @sp sp sp + 2 pc @ip ip ip + 2 this instruction is useful when implementing threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 16 2f example: the diagram below shows an example of how to use an exit statement. ip data address data 50 51 address data 60 00 memory stack 0050 before 0022 0040 pc 22 iph ipl data ip address data 60 address data memory stack pcl old pch exit 0043 0020 0110 pc main 140 20 21 22 after 00 50
S3C84H5/f84h5 instruction set 6-43 idle ? idle operation idle operation: (see description) the idle instruction stops the cpu clock while allowing the system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but it does not stop the system clock.
instruction set S3C84H5/f84h5 6-44 inc ? increment inc dst operation: dst dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 r0 = 1ch inc 00h register 00h = 0dh inc @r0 r0 = 1bh, register 01h = 10h in the first example, if the destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the second example shows the effect an inc instru ction has on the register at the location 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of the register 1bh from 0fh to 10h.
S3C84H5/f84h5 instruction set 6-45 incw ? increment word incw dst operation: dst dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 r0 = 1ah, r1 = 03h incw @r1 register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in the register r0 and 02h in the register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in the register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of the general register 03h from 0ffh to 00h and the register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, it is recommended to use the incw instruction as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop
instruction set S3C84H5/f84h5 6-46 iret ? interrupt return iret iret (normal) ret (fast) operation: flags @sp pc ? ip sp sp + 1 flags flags' pc @sp fis 0 sp sp + 2 sym(0) 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 12 bf iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupt are enabled. when an interrupt occurs, the program counter and the instruction pointer are swapped. this causes the pc to jump to the address 100h and the ip to keep the return address. the last instruction in the service ro utine is normally a jump to iret at the address ffh. this loads the instruction pointer with 100h "again" and causes the program counter to jump back to the main progra m. now, the next interr upt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note : in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last tow instruction. the iret cannot be immediately proceeded by an instruction which clears the interrupt status (as with a reset of the ipr register).
S3C84H5/f84h5 instruction set 6-47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes: 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the 3-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h:secs jp c,label_w label_w = 1000h, pc = 1000h jp @00h pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h.
instruction set S3C84H5/f84h5 6-48 jr ? jump relative jr cc,dst operation: if cc is true, pc pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the jr instruction is executed. (see the list of condition codes at the beginning of this chapter). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note: in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits in length. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x pc = 1ff7h if the carry flag is set (that is, if the condition code is ?true?), the statemen t "jr c,label_x" will pass control to the statement whose address is currently in the program counter. otherwise, the program instruction following the jr will be executed.
S3C84H5/f84h5 instruction set 6-49 ld ? load ld dst,src operation: dst src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r
instruction set S3C84H5/f84h5 6-50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h r0 = 10h ld r0,01h r0 = 20h, register 01h = 20h ld 01h,r0 register 01h = 01h, r0 = 01h ld r1,@r0 r1 = 20h, r0 = 01h ld @r0,r1 r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h register 00h = 20h, register 01h = 20h ld 02h,@00h register 02h = 20h, register 00h = 01h ld 00h,#0ah register 00h = 0ah ld @00h,#10h register 00h = 01h, register 01h = 10h ld @00h,02h register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 register 31h = 0ah, r0 = 01h, r1 = 0ah
S3C84H5/f84h5 instruction set 6-51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) src(b) or dst(b) src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note: in the second byte of the instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 r0 = 07h, register 00h = 05h ldb 00h.0,r0 r0 = 06h, register 00h = 04h in the first example, the destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in the register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of the register r0 to the specified bit (bit zero) of the destination register, leaving 04h in the general register 00h.
instruction set S3C84H5/f84h5 6-52 ldc/lde ? load memory ldc dst,src lde dst,src operation: dst src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes "irr" or "rr" values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes: 1. the source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0?1. 2. for the formats 3 and 4, the destination "xs [rr]" and the source address "xs [rr]" are both one byte. 3. for the formats 5 and 6, the destination "xl [rr] and the source address "xl [rr]" are both two bytes. 4. the da and the r source values for the formats 7 and 8 are used to address program memory. the second set of values, used in the formats 9 and 10, are used to address data memory. 5. lde instruction can be used to read/write the data of 64-kbyte data memory.
S3C84H5/f84h5 instruction set 6-53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 contents of program memory location 0104h; ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 contents of external data memory location 0104h; ; r0 = 2ah, r2 = 01h, r3 = 04h ldc @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2); r0, r2, r3 no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2); r0, r2, r3 no change ldc r0,#01h[rr2] ; r0 contents of program memory location 0105h ; (01h + rr2); r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 contents of external data memory location 0105h ; (01h + rr2); r0 = 7dh, r2 = 01h, r3 = 04h ldc #01h[rr2],r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 contents of program memory location 1104h ; (1000h + 0104h); r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 contents of external data memory location 1104h ; (1000h + 0104h); r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 contents of program memory location 1104h ; r0 = 88h lde r0,1104h ; r0 contents of external data memory location 1104h; ; r0 = 98h ldc 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h; (1105h) 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h; (1105h) 11h note: the ldc and the lde instructions are not supported by masked rom type devices.
instruction set S3C84H5/f84h5 6-54 ldcd/lded ? load memory and decrement ldcd dst,src lded dst,src operation: dst src rr rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd refers to program memory and lded refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one; ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 rr6 ? 1); ; r8 = 0ddh, r6 = 10h, r7 = 32h note: lded instruction can be used to read/write the data of 64-kbyte data memory.
S3C84H5/f84h5 instruction set 6-55 ldci/ldei ? load memory and increment ldci dst,src ldei dst,src operation: dst src rr rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 rr6 + 1); ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 rr6 + 1); ; r8 = 0ddh, r6 = 10h, r7 = 34h note: ldei instruction can be used to read/write the data of 64-kbyte data memory. `
instruction set S3C84H5/f84h5 6-56 ldcpd/ldepd ? load memory with pre-decrement ldcpd dst,src ldepd dst,src operation: rr rr ? 1 dst src these instructions are used for block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 rr6 ? 1) ; 77h (the contents of r0) is loaded into program memory ; location 2fffh (3000h ? 1h); ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 rr6 ? 1) ; 77h (the contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h); note: ldepd instruction can be used to read/write the data of 64-kbyte data memory.
S3C84H5/f84h5 instruction set 6-57 ldcpi/ldepi ? load memory with pre-increment ldcpi dst,src ldepi dst,src operation: rr rr + 1 dst src these instructions are used for block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 brr6 + 1) ; 7fh (the contents of r0) is loaded into program memory ; location 2200h (21ffh + 1h); ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 brr6 + 1) ; 7fh (the contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h); ; r0 = 7fh, r6 = 22h, r7 = 00h note: ldepi instruction can be used to read/write the data of 64-kbyte data memory.
instruction set S3C84H5/f84h5 6-58 ldw ? load word ldw dst,src operation: dst src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h,and register 03h = 0fh ldw rr6,rr4 r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 r2 = 03h, r3 = 0fh, ldw 04h,@01h register 04h = 03h, register 05h = 0fh ldw rr6,#1234h r6 = 12h, r7 = 34h ldw 02h,#0fedh register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h and 03h into the destination word 00h and 01h. this leaves the value 03h in the general register 00h and the value 0fh in the register 01h. other examples show how to use the ldw instruction with various addressing modes and formats.
S3C84H5/f84h5 instruction set 6-59 mult ? multiply (unsigned) mult dst,src operation: dst dst src the 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if the result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 22 84 rr r 22 85 rr ir 22 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h register 00h = 00h, register 01h = 0c0h mult 00h, #30h register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h, 02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16-bit product, 0120h, is stored in the register pair 00h, 01h.
instruction set S3C84H5/f84h5 6-60 next ? next next operation: pc @ip ip ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is th en incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 0f example: the following diagram shows an example of how to use the next instruction. data 01 30 before after 0045 1p address data 0130 pc 43 44 45 address h address l address h address data memory 130 routine 0043 1p address data 0120 pc 43 44 45 address h address l address h address data memory 120 next
S3C84H5/f84h5 instruction set 6-61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to affect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is executed in a program, no operation occurs. instead, there happens a delay in instruction execution time which is of approximately one machine cycle per each nop instruction encountered.
instruction set S3C84H5/f84h5 6-62 or ? logical or or dst,src operation: dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah or r0,r1 r0 = 3fh, r1 = 2ah or r0,@r2 r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h register 00h = 3fh, register 01h = 37h or 01h,@00h register 00h = 08h, register 01h = 0bfh or 00h,#02h register 00h = 0ah in the first example, if the working register r0 contains the value 15h and the register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in the destination register r0. other examples show the use of the logical or instruction with various addressing modes and formats.
S3C84H5/f84h5 instruction set 6-63 pop ? pop from stack pop dst operation: dst @sp sp sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h register 00h = 55h, sp = 00fch pop @00h register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, the general register 00h contains the value 01h. the statement "pop 00h" loads the contents of the location 00fbh (55h) into the destination register 00h and then increments the stack pointer by one. the register 00h then contains the value 55h and the sp points to the location 00fch.
instruction set S3C84H5/f84h5 6-64 popud ? pop user stac k (decrementing) popud dst,src operation: dst src ir ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h register 00h = 41h, register 02h = 6fh, register 42h = 6fh 02h if the general register 00h contains the value 42h and the register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of the register 42h into the destination register. the user stack pointer is then decremented by one, leaving the value 41h.
S3C84H5/f84h5 instruction set 6-65 popui ? pop user stack (incrementing) popui dst,src operation: dst src ir ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h register 00h = 02h, register 01h = 70h, register 02h = 70h if the general register 00h contains the value 01h and the register 01h the value 70h, the statement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (the register 00h) is then incremented by one, changing its value from 01h to 02h.
instruction set S3C84H5/f84h5 6-66 push ? push to stack push src operation: sp sp ? 1 @sp src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and the general register 40h the value 4fh, the statement "pus h 40h" decrements the stack po inter from 0000 to 0ffffh. it then loads the contents of the register 40h into the location 0ffffh and adds this new value to the top of the stack.
S3C84H5/f84h5 instruction set 6-67 pushud ? push user stack (decrementing) pushud dst,src operation: ir ir ? 1 dst src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (the register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer.
instruction set S3C84H5/f84h5 6-68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ir + 1 dst src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (the register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer.
S3C84H5/f84h5 instruction set 6-69 rcf ? reset carry flag rcf rcf operation: c 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero.
instruction set S3C84H5/f84h5 6-70 ret ? return ret operation: pc @sp sp sp + 2 the ret instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement to be executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 af example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret pc = 101ah, sp = 00feh the ret instruction pops the contents of the stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in the location 00feh (1ah) into the pc's low byte and the instruction at the location 101ah is executed. the stack pointer now points to the memory location 00feh.
S3C84H5/f84h5 instruction set 6-71 rl ? rotate left rl dst operation: c dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag, as shown in the figure below. 70 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h register 00h = 55h, c = "1" rl @01h register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry (c) and the overflow (v) flags.
instruction set S3C84H5/f84h5 6-72 rlc ? rotate left through carry rlc dst operation: dst (0) c c dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c), and the initial value of the carry flag replaces bit zero. 70 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h register 00h = 54h, c = "1" rlc @01h register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of the register 00h, leaving the value 55h (01010101b). the msb of the register 00h resets the carry flag to "1" and sets the overflow flag.
S3C84H5/f84h5 instruction set 6-73 rr ? rotate right rr dst operation: c dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 70 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h register 00h = 98h, c = "1" rr @01h register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if the general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and the overflow flag are also set to "1".
instruction set S3C84H5/f84h5 6-74 rrc ? rotate right through carry rrc dst operation: dst (7) c c dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (msb). 70 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h register 00h = 2ah, c = "1" rrc @01h register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if the general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in the destination register 00h. the sign flag and the overflow flag are both cleared to "0".
S3C84H5/f84h5 instruction set 6-75 sb0 ? select bank 0 sb0 operation: bank 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting the bank 0 register addressing.
instruction set S3C84H5/f84h5 6-76 sb1 ? select bank 1 sb1 operation: bank 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file. note: bank 1 is not implemented in some ks88-series microcontrollers. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to ?1?, selectin the bank 1 register addressing (if bank 1 is implemented in the micr ocontrooler?s internla register file).
S3C84H5/f84h5 instruction set 6-77 sbc ? subtract with carry sbc dst,src operation: dst dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a ?borrow? format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 r1 = 0ch, r2 = 03h sbc r1,@r2 r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h register 01h = 1ch, register 02h = 03h sbc 01h,@02h register 01h = 15h, register 02h = 03h, register 03h = 0ah sbc 01h,#8ah register 01h = 95h; c, s, and v = "1" in the first example, if the working register r1 contains the value 10h and the register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in the register r1.
instruction set S3C84H5/f84h5 6-78 scf ? set carry flag scf operation: c 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to ?1?.
S3C84H5/f84h5 instruction set 6-79 sra ? shift right arithmetic sra dst operation: dst (7) dst (7) c dst (0) dst (n) dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6. 70 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h register 00h = 0cd, c = "0" sra @02h register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if the general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in the register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in the destination register 00h.
instruction set S3C84H5/f84h5 6-80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3?7) src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3?7) src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4?7) src (4?7), rp0 (3) 0 rp1 (4?7) src (4?7), rp1 (3) 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets the register pointer 0 (rp0) at the location 0d6h to 40h and the register pointer 1 (rp1) at the location 0d7h to 48 h. the statement "srp0 #50h" would set rp0 to 50h, and the statement "srp1 #68h" would set rp1 to 68h. note: before execute the stop instruction, you must set the stpcon register as ?10100101b?. otherwise the stop instruction will not execute.
S3C84H5/f84h5 instruction set 6-81 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillati on stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontr oller operations.
instruction set S3C84H5/f84h5 6-82 sub ? subtract sub dst,src operation: dst dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a ?borrow?. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 r1 = 0fh, r2 = 03h sub r1,@r2 r1 = 08h, r2 = 03h sub 01h,02h register 01h = 1eh, register 02h = 03h sub 01h,@02h register 01h = 17h, register 02h = 03h sub 01h,#90h register 01h = 91h; c, s, and v = "1" sub 01h,#65h register 01h = 0bch; c and s = "1", v = "0" in the first example, if he working register r1 contains the value 12h and if the register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in the destination register r1.
S3C84H5/f84h5 instruction set 6-83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and the upper four bits of the destination operand are swapped. 70 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h register 00h = 0e3h swap @02h register 02h = 03h, register 03h = 4ah in the first example, if the general register 00h contains the value 3eh (00111110b), the statement "swap 00h" swaps the lower and the upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b).
instruction set S3C84H5/f84h5 6-84 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and the source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 register 00h = 2bh, z = "0" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation.
S3C84H5/f84h5 instruction set 6-85 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and the source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h register 00h = 2bh, z = "1" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation.
instruction set S3C84H5/f84h5 6-86 wfi ? wate for interrupt wfi operation: the cpu is effectively halted before an interrupt occurs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt)
S3C84H5/f84h5 instruction set 6-87 xor ? logical exclusive or xor dst,src operation: dst dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different. otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 r0 = 0c5h, r1 = 02h xor r0,@r1 r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h register 00h = 29h, register 01h = 02h xor 00h,@01h register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h register 00h = 7fh in the first example, if the working register r0 contains the value 0c7h and if the register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0.
S3C84H5/f84h5 clock circuit 7-1 7 clock circuit overview the clock frequency generated for the main clock of S3C84H5/f84h5 by an external crystal can range from 1 mhz to 10 mhz. the maximum cpu clock frequency is 10 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. also the subsys tem clock frequency fo r the watch timer by an external crystal can range from 30 khz to 35 khz. the xt in and xt out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an external clock source) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (fxx divided by 1, 2, 8, or 16) ? system clock control register, clkcon ? oscillator cont rol register, osccon and stop control regi ster, stpcon x in x out c 1 c2 S3C84H5 s3f84h5 figure 7-1. main os cillator circuit (crystal or ceramic oscillator) 32.768 khz S3C84H5 s3f84h5 xt in xt out figure 7-2. sub-system oscillator circuit (crystal oscillator)
clock circuit S3C84H5/f84h5 7-2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is rele ased, and the oscillator is started, by a reset operation or an external interrupt (with rc delay noise filter). ), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. ? in idle mode, the internal clock signal is gated to the cpu, but not to interrupt structure, timers and timer/ counters. idle mode is released by a reset or by an external or internal interrupt. 1/8-1/4096 frequency dividing circuit stop release selector 1 f x f xt stop sub-system oscillator circuit int osccon.0 osccon.3 osccon.2 selector 2 stpcon stop osc inst. f xx clkcon.4-.3 cpu clock stop watch timer basic timer timer/counter watch timer (fxx/256) uart a/d converter system clock idle instruction 1/1 1/16 1/2 1/8 main-ststem oscillator circuit figure 7-3. system clock circuit diagram
S3C84H5/f84h5 clock circuit 7-3 system clock control register (clkcon) the system clock control register, clkcon, is located in set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator frequency divide-by value after the main oscillator is ac tivated, and the f xx/16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed fxx/8, fxx/2, or fxx/1. xt in xt out 32.768 khz S3C84H5 s3f84h5 figure 7-4. system clock c ontrol register (clkcon)
clock circuit S3C84H5/f84h5 7-4 oscillator control register (osccon) f2h, set 1, bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 lsb not used (must keep always 0) system clock selection bit: 0 = main oscillator select 1 = subsystem oscillator select not used (must keep always 0) subsystem oscillator control bit: 0 = subsystem oscillator run 1 = subsystem oscillator stop mainsystem oscillator control bit: 0 = mainsystem oscillator run 1 = mainsystem oscillator stop note: when the cpu is operated with fxt (sub-oscillation clock), it is possible to use the stop then the oscillation stabilization time is 62.5 ((1/32768) x 128 x 16) ms + 100 ms. here the warm-up time is from the time that the stop release signal activates to the time that basic timer starts counting. instruction but in this case before using stop instruction, you must select fxx/128 for basic timer counter input clock. msb figure 7-5. oscillator c ontrol register (osccon) stop control register (stopcon) e5h, set 1,bank 0, r/w .7 .6 .5 .4 .3 .2 .1 .0 lsb stop control bits: other values = disable stop instruction 10100101 = enable stop instruction msb figure 7-6. stop contro l register (stopcon)
S3C84H5/f84h5 reset and power-down 8-1 8 reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings S3C84H5/f84h5 into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pi n must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default ha rdware values in summary, the following sequence of events occurs during a reset operation: ? interrupt is disabled. ? the watchdog function (basic timer) is enabled. ? ports 0-3 are set to input mode ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscilla tion stabilization time in terval has elapsed, the in struction stored in rom location 0100h (and 0101h) is fetched and executed. normal mode reset operation in normal (masked rom) mode, the test pin is tied to v ss . a reset enables access to the 16-kbyte on-chip rom. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
reset and power-down S3C84H5/f84h5 8-2 hardware reset values table 8-1, 8-2, and 8-3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined after a reset. ? a dash ("?") means that the bit is either not used or not mapped, but read 0 is the bit value. table 8-1. S3C84H5/f84h5 set 1 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 timer b control register tbcon 208 d0h 0 0 0 0 0 0 0 0 timer b data register (high byte) tbdatah 209 d1h 1 1 1 1 1 1 1 1 timer b data register (low byte) tbdatal 210 d2h 1 1 1 1 1 1 1 1 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x x x x x system mode register sym 222 deh 0 0 0 x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0
S3C84H5/f84h5 reset and power-down 8-3 table 8-2. S3C84H5/f84h5 set 1, bank 0 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 location e4h is not mapped stop control register stopcon 229 e5h 0 0 0 0 0 0 0 0 port 0 control register (high byte) p0con 230 e6h 0 0 0 0 0 0 0 0 location fbh is not mapped port 1 control register (high byte) p1conh 232 e8h 0 0 0 0 0 0 0 0 port 1 control register (low byte) p1conl 233 e9h 0 0 0 0 0 0 0 0 port 1 interrupt pending register p1intpnd 234 eah 0 0 0 0 0 0 0 0 port 1 interrupt control register p1int 235 ebh 0 0 0 0 0 0 0 0 port 2 control register (high byte) p2conh 234 ech 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 235 edh 0 0 0 0 0 0 0 0 location eeh is not mapped port 3 control register (low byte) p3conl 239 efh 0 0 0 0 0 0 0 0 location f0h, f1h is not mapped oscillator control register osccon 242 f2h 0 0 0 0 0 0 0 0 location fbh is not mapped uart pending register uartpnd 244 f4h 0 0 0 0 0 0 0 0 uart data register udata 245 f5h 1 1 1 1 1 1 1 1 uart control register uartcon 246 f6h 0 0 0 0 0 0 0 0 a/d converter control register adcon 247 f7h 0 0 0 0 0 0 0 0 a/d converter data register(high byte) addatah 248 f8h 0 0 0 0 0 0 0 0 a/d converter data register(low byte) addatal 249 f9h 0 0 0 0 0 0 0 0 port 2 pull-up enable control register p2pur 250 fah 0 0 0 0 0 0 0 0 location fbh is not mapped location fch is factory use only. basic timer counter register btcnt 253 fdh 0 0 0 0 0 0 0 0 location feh is not mapped. interrupt priority register ipr 255 ffh x x x x x x x x
reset and power-down S3C84H5/f84h5 8-4 table 8-3. S3C84H5/f84h5 set 1, bank 1 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 timer a, 1 interrupt pending register tintpnd 224 e0h 0 0 0 0 0 0 0 0 timer a control register tacon 225 e1h 0 0 0 0 0 0 0 0 timer a data register tadata 226 e2h 1 1 1 1 1 1 1 1 timer a counter register tacnt 227 e3h 0 0 0 0 0 0 0 0 timer 1(0) data register (high byte) t1datah0 228 e4h 1 1 1 1 1 1 1 1 timer 1(0) data register (low byte) t1datal0 229 e5h 1 1 1 1 1 1 1 1 timer 1(1) data register (high byte) t1datah1 230 e6h 1 1 1 1 1 1 1 1 timer 1(1) data register (low byte) t1datal1 231 e7h 1 1 1 1 1 1 1 1 timer 1(0) control register t1con0 232 e8h 0 0 0 0 0 0 0 0 timer 1(1) control register t1con1 233 e9h 0 0 0 0 0 0 0 0 timer 1(0) counter register (high byte) t1cnth0 234 eah 0 0 0 0 0 0 0 0 timer 1(0) counter register (low byte) t1cntl0 235 ebh 0 0 0 0 0 0 0 0 timer 1(1) counter register (high byte) t1cnth1 236 ech 0 0 0 0 0 0 0 0 timer 1(1) counter register (low byte) t1cntl1 237 edh 0 0 0 0 0 0 0 0 uart baud rate data register (high) brdatah 238 eeh 1 1 1 1 1 1 1 1 uart baud rate data register (low) brdatal 239 efh 1 1 1 1 1 1 1 1 sio pre-scalar register siops 240 f0h 0 0 0 0 0 0 0 0 sio data register siodata 241 f1h 0 0 0 0 0 0 0 0 serial i/o control register siocon 242 f2h 0 0 0 0 0 0 0 0 pwm data register (high) pwmdatah 243 f3h 0 0 0 0 0 0 0 0 pwm data register (low) pwmdatal 244 f4h 0 0 0 0 0 0 0 0 pwm control register pwmcon 245 f5h 0 0 - 0 0 0 0 0 location f6h, f7h is not mapped watch timer control register wtcon 248 f8h 0 0 0 0 0 0 0 0 location f9h?ffh are not mapped
S3C84H5/f84h5 reset and power-down 8-5 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. th at is, the on-chip main oscillator stops an d the supply current is re duced to less than 3 a except for the current consumption of lvr (low voltage reset) circuit. all system functions stop when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset or by interrupts. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. using reset to release stop mode stop mode is released when the reset signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the progra mmed oscillation stabiliz ation interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h (and 0101h). using an external interr upt to release stop mode external interrupts with an rc-delay noise filter circuit can be used to release stop mode. which interrupt you can use to release stop mode in a given situation depends on the microcontroller's current internal operating mode. the external interrupts in the S3C84H5/f84h5 interrupt structure that can be used to release stop mode are: ? external interrupts p1.0-p1.3 (int0-int3). please note the following conditions for stop mode release: ? if you release stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? when the stop mode is released by external interrupt, the clkcon.4 and clkcon.3 bit-pair setting remains unchanged and the currently selected clock value is used. ? the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed.
reset and power-down S3C84H5/f84h5 8-6 how to enter into stop mode there are two steps to enter into stop mode: 1. handling stopcon register to appropriate value (10100101b). 2. writing stop instruction (keep the order). idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu, but all peripherals timers remain active. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slow clock fxx/16 because clkcon.4 and clkcon.3 are cleared to ?00b?. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.4 and clkcon.3 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction immediately following the one that initiated idle mode is executed.
S3C84H5/f84h5 i/o ports 9-1 9 i/o ports overview the S3C84H5/f84h5 microcontroller has five bit-programmable i/o ports, p0-p3. this gives a total of 22 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9-1 gives you a general overview of the S3C84H5/f84h5 i/o port functions. table 9-1. S3C84H5/f84h5 po rt configuration overview port configuration options 0 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternately, p0.0~p0.3 can be used as ad0~ad3. 1 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up resistor. alternatively, p1.0~p1.5 can be used as in t0~int3, taout, tack,tacap, t1out0, t1ck1 t1cap1,ad5,ad6. 2 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p2.0~p2.7 can be used adc4,a dc7,si,t1cap0,t1out1,t1ck0,so,sck,rxd,txd, tbpwm,pwm 3 bit programmable port; input or output mode selected by software; input or push-pull, n-channel open-drain output. software assignable pull-up.. note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. (reter to page 9-14) after you have finished your program and before assembling, you have to remove these three commands. .org 100h sb1 ; extra command only for debugging ld 0f7h,#5fh ; extra command only for debugging sb0 ; extra command only for debugging
i/o ports S3C84H5/f84h5 9-2 port data registers table 9-2 gives you an overview of the register locations of all seven S3C84H5/f84h5 i/o port data registers. data registers for ports 0, 1, 2, and 3 have the general format shown in table 9-2. table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1, bank 0 r/w port 1 data register p1 225 e1h set 1, bank 0 r/w port 2 data register p2 226 e2h set 1, bank 0 r/w port 3 data register p3 227 e3h set 1, bank 0 r/w
S3C84H5/f84h5 i/o ports 9-3 port 0 port 0 is an 4-bit i/o port that you can use two ways: ? general-purpose digital i/o ? alternative function: ad0~ad3 port 0 is accessed directly by writing or reading the port 0 data register, p0 at location e0h in set 1, bank 0. port 0 control register (p0con) port 0 has one 8-bit control registers: p0con for p0.0?p0.3. a reset clears the p0con registers to ?00h?, configuring all pins to input modes. you use control registers settings to select input or output mode (push-pull) and enable the alternative functions. when programming the port, please remember that any alternative peripheral i/o function you configure using the port 0 control registers must also be enabled in the associated peripheral module. port 0 control register, low byte (p0con) e6h, set1, bank0, r/w, reset value="00h" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p0.3/adc3configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = alternative function mode;ad3 input [.5-.4] p0.2/ad2 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = alternative function mode: adc2 input [.3-.2] p0.1/ adc1 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = alternative function mode: adc1 input [.1-.0] p0.0/adc0 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = alternative function mode: adc0 input figure 9-1. port 0 low byte control register (p0con)
i/o ports S3C84H5/f84h5 9-4 port 1 port 1 is a 6-bit i/o port with individually configurable pins that you can use two ways: ? general-purpose digital i/o ? alternative function: int0~int3, taout, tack, tacap, t1out0,t1ck1,t1cap1,ad5,ad6 port 1 is accessed directly by writing or reading the port 1 data register, p1 at location e1h in set 1, bank 0. port 1 control register (p1conh, p1conl) port 1 has two 6-bit control registers: p1conh for p1.4?p1.5 and p1conl for p1.0?p1.3. a reset clears the p1conh and p1conl registers to ?00h?, configuring all pins to input modes. you use control registers settings to select input or output mode (push-pull) and enable the alternative functions. when programming the port, please remember that any alte rnative peripheral i/o function you configure using the port 1 control registers must also be enabled in the associated peripheral module. port 1 interrupt enable, pending, and edge selection registers (p1int,p1intpnd) to process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register p1int (eah, set1 bank 0), the port 1 interrupt pending bits p1intpnd (ebh, set1 bank 0). the port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the p1intpnd1.3-.0 regi ster at regular intervals. when the interrup t enable bit of any port 1 pin is "1", a rising or falling edge at th at pin will genera te an interrupt request. the corresponding p1intpnd1 bit is then automatically set to "1" and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding p1intpnd1 bit.
S3C84H5/f84h5 i/o ports 9-5 port 1 control register, high byte (p1conh) e8h, set1, bank0, r/w, reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.4] not used (must keep always 0) [.3-.2] p1.5/t1cap1/ad6 configuration bits 0 0 = input mode; t1cap1 input 0 1 = input mode with pull-up; t1cap1 input 1 0 = push-pull output mode 1 1 = alternative function mode: ad6 [.1-.0] p1.4/t1ck1/ad5 configuration bits 0 0 = input mode; t1ck1 input 0 1 = input mode with pull-up ; t1ck1 input 1 0 = push-pull output mode 1 1 = alternative function mode: ad5 figure 9-2. port 1 high-byte control register (p1conh)
i/o ports S3C84H5/f84h5 9-6 port 1 control register, low byte (p1conl) e9h, set1, bank0, r/w, reset value="00h" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p1.3/t1out0/int3 configuration bits 0 0 = input mode; interrupt input (int3) 0 1 = input mode with pull-up; interrupt input (int3) 1 0 = push-pull output mode 1 1 = alternative function mode: t1out0 output [.5-.4] p1.2/tacap/int2 configuration bits 0 0 = input mode; interrupt input (int2); tacap 0 1 = input mode with pull-up; interrupt input (int2);tacap 1 0 = push-pull output mode 1 1 = alternative function mode: not used [.3-.2] p1.1/tack/buz/int1 configuration bits 0 0 = input mode; interrupt input (int1); tack 0 1 = input mode with pull-up ; interrupt input (int1); tack 1 0 = push-pull output mode 1 1 = alternative function mode: buz output [.1-.0] p1.0/taout/int0 configuration bits 0 0 = input mode; interrupt input (int0) 0 1 = input mode with pull-up; interrupt input 1 0 = push-pull output mode 1 1 = alternative function mode: taout output figure 9-3. port 1 low-byte control register (p1conl)
S3C84H5/f84h5 i/o ports 9-7 port 1 interrupt pending register (p1intpnd) eah, set1, bank0, r/w, reset value="00h" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.4] not used for S3C84H5/f84h5 [.3] p1.3/int3 interrupt pending bit 0 = interrupt request is not pending,pending bit clear when write 0 1 = interrupt request is pending [.2] p1.2/int2 interrupt pending bit 0 = interrupt request is not pending,pending bit clear when write 0 1 = interrupt request is pending [.1] p1.1/int1 interrupt pending bit 0 = interrupt request is not pending,pending bit clear when write 0 1 = interrupt request is pending [.0] p1.0/int0 interrupt pending bit 0 = interrupt request is not pending,pending bit clear when write 0 1 = interrupt request is pending figure 9-4. port 1 interrupt pending register (p1intpnd)
i/o ports S3C84H5/f84h5 9-8 port 1 interrupt enable register (p1int) ebh, set1, bank0, r/w, reset value="00h" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p1.3's interrupt enable/disable selection bit 0x = disable interrupt 10 = enable interrupt; falling edge 11 = enable interrupt; rising edge [.5-.4] p1.2s interrupt enable/disable selection bit 0x = disable interrupt 10 = enable interrupt; falling edge 11 = enable interrupt; rising edge [.3-.2] p1.1's interrupt enable/disable selection bit 0x = disable interrupt 10 = enable interrupt; falling edge 11 = enable interrupt; rising edge [.1-.0] p1.0's interrupt enable/disable selection bit 0x = disable interrupt 10 = enable interrupt; falling edge 11 = enable interrupt; rising edge figure 9-5. port 1 interrupt enable register (p1int) port 2 port 2 is an 8-bit i/o port with individually configurable pins. port 2 pins are accessed directly by writing or reading the port 2 data register, p2 at location e2h in set 1, ba nk 0. p2.0?p2.7 can serve as digital inputs, outputs (push pull) or you can configure the following alternative functions: ? general-purpose digital i/o ? lternative function: adc4,adc7,si, t1cap0,t1out1,t1ck0,tbpwm,pwm port 2 control register (p2conh, p2conl) port 2 has two 8-bit control registers: p2conh for p2.4?p2.7 and p2conl for p2.0?p2.3. a reset clears the p2conh and p2conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode (push-pull) and enable the alternative functions. when programming the port, please remember that any alternative peripheral i/o function you configure using the port 2 control registers must also be enabled in the associated peripheral module. port 2 pull-up control registers (p2pur) using the port 2 pull-up control register, p2pur (fa, set1,bank0), you can configure pull-up resistors to individual port 0 pins.
S3C84H5/f84h5 i/o ports 9-9 port 2 control register, high byte (p2conh) ech, set1, bank0, r/w, reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p2.7/txd configuration bits 0 0 = input mode 0 1 = alternative function mode; not used 1 0 = push-pull output mode 1 1 = alternative function mode; txd output [.5-.4] p2.6/rxd configuration bits 0 0 = input mode 0 1 = alternative function mode; not used 1 0 = push-pull output mode 1 1 = alternative function mode; rxd output [.3-.2] p2.5/sck configuration bits 0 0 = input mode 0 1 = alternative function mode; not used 1 0 = push-pull output mode 1 1 = alternative function mode; sck output [.1-.0] p2.4/so configuration bits 0 0 = input mode 0 1 = alternative function mode; not used 1 0 = push-pull output mode 1 1 = alternative function mode; so output figure 9-6. port 2 high-byte control register (p2conh)
i/o ports S3C84H5/f84h5 9-10 port 2 control register, low byte (p2conl) edh, set1, bank0, r/w, reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p2.3/ad7/si configuration bits 0 0 = input mode; si 0 1 = alternative function mode; not used 1 0 = push-pull output mode 1 1 = alternative function mode; ad7 [.7-.6] p2.2/ad4/t1out1 configuration bits 0 0 = input mode 0 1 = alternative function mode; t1out1 1 0 = push-pull output mode 1 1 = alternative function mode; ad4 [.7-.6] p2.1/pwm/t1cap0 configuration bits 0 0 = input mode; t1cap0 0 1 = alternative function mode; t1cap0 1 0 = push-pull output mode 1 1 = alternative function mode; pwm [.7-.6] p2.0/tbpwm/t1ck0 configuration bits 0 0 = input mode;t1ck0 0 1 = alternative function mode; t1ck0 1 0 = push-pull output mode 1 1 = alternative function mode; tbpwm figure 9-7. port 2 low-byte control register (p2conl)
S3C84H5/f84h5 i/o ports 9-11 port 2 pull-up control register (p2pur) fah, set1, bank0, r/w, reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7] p2.7/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.6] p2.6/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.5] p2.5/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.4] p2.4/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.3] p2.3/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.2] p2.2/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.1] p2.1/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable [.0] p2.0/pull-up resistor enable/disable 0 = pull-up resistor disable 1 = pull-up resistor enable figure 9-8. port 2 pull-up control register (p2pur)
i/o ports S3C84H5/f84h5 9-12 port 3 port 3 is an 8-bit i/o port that can be used for general-purpose digital i/o. the pins are accessed directly by writing or reading the port 3 data register, p3 at location e3h in set 1, bank 0. p3.0?p3.3 can serve as inputs, outputs (push pull). port 3 control register ( p3conl) port 3 has two 8-bit control registers: p3conh for p3.4?p3.7 and p3conl for p3.0?p3.3. a reset clears the p3conh and p3conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode (push-pull,open-drain) and enable the alternative functions. when programming the port, please remember that any alte rnative peripheral i/o function you configure using the port 3 control registers must also be enabled in the associated peripheral module. port 3 control register, low byte (p3conl) efh, set1, bank0, r/w, reset value="00" .7 .6 .5 .4 .3 .2 .1 .0 msb lsb [.7-.6] p3.3 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = n-channel open-drain output [.5-.4] p3.2 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = n-channel open-drain output [.3-.2] p3.1 configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = n-channel open-drain output [.1-.0] p3.0/ configuration bits 0 0 = input mode 0 1 = input mode with pull-up 1 0 = push-pull output mode 1 1 = n-channel open-drain output figure 9-9. port 3 low-byte control register (p3conl)
S3C84H5/f84h5 i/o ports 9-13 programming tip ? using the timer a org 0000h vector 0c0h,tamc_int vector 0c2h,taov_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt sym ld imr,#00000010b ; enable irq1 interrupt ld sph,#00000000b ; set stack area ld spl,#00000000b ld btcon,#10100011b ; disable watch-dog ld p1conl,#0abh ; enable taout output sb1 ld tadata,#80h ld tacon,#01001010b ; match interrupt enable ; 6.55 ms duration (10 mhz x?tal) sb0 ei main: ? ? main routine ? ? jr t,main tamc_int: ? ? interrupt service routine ? ? iret taov_int: ? interrupt service routine ? iret .end
i/o ports S3C84H5/f84h5 9-14 programming tip ? using ports org 0100h initial: sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) di ld spl,#00000000b ld btcon,#10100011b ; disable watch-dog ld clkcon,#18h ld p0con,#0aah ; port0 push-pull output ld p1conh,#0aah ; port1 push-pull output ld p1conl,#0aah ; port1 push-pull output ld p2conh,#0aah ; port2 push-pull output ld p2conl,#0aah ; port2 push-pull output ld p3conl,#0aah ; port3 push-pull output main: ? ? ? xor p0,#0fh xor p1,#03fh xor p2,#0ffh xor p3,#0fh ? ? ? jr t,main .end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 basic timer 10-1 10 basic timer overview basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillat ion stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (fxx divided by 4096, 1024 or 128) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to '00h'. this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, write the signature code '1010b' to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers, write a "1" to btcon.0.
basic timer S3C84H5/f84h5 10-2 basic timer control register (btcon) d3h, set 1, r/w lsb msb.7.6.5.4.3.2.1.0 divider clear bit: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bit: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = fxx/1 (not used) watchdog timer enable bit: 1010b = disable watchdog function other value = enable watchdog function figure 10-1. basic timer c ontrol register (btcon)
S3C84H5/f84h5 basic timer 10-3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than "1010b". (the "1010b" value disables the watchdog function.) a reset clears btcon to "00h", automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. the cpu is reset whenever a basic timer counter overflow occurs, during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. to do this, the btcnt value must be cleared (by writing a ?1? to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basi c timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilizati on interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a re set or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic time r counter will increase at the rate of fxx/4096. if an external interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. when a btcnt.4 overflow occurs, normal cpu operation resumes.
basic timer S3C84H5/f84h5 10-4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux fxx/4096 div fxx/1024 fxx/128 fxx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic ti mer block diagram
S3C84H5/f84h5 8-bit timer a/b 11-1 11 8-bit timer a/b 8-bit timer a overview the 8-bit timer a is an 8-bit general-purpose timer/counter. timer a has three operating modes, you can select one of them using the appropriate tacon setting: ? interval timer mode (toggle output at taout pin) ? capture input mode with a rising or falling edge trigger at the tacap pin ? pwm mode (tapwm) timer a has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer ? external clock input pin (tack) ? 8-bit counter (tacnt), 8-bit comparator, and 8-bit reference data register (tadata) ? i/o pins for capture input (tacap) or pwm or match output (taout) ? timer a overflow interrupt (irq1, vector c2h) and match/capture interrupt (irq1, vector c0h) generation ? timer a control register, tacon (set 1, bank1, e1h, read/write)
8-bit timer a/b S3C84H5/f84h5 11-2 function description timer a interrupts (irq1, vectors c0h and c2h) the timer a module can generate two interrupts: the timer a overflow interrupt (taovf), and the timer a match/ capture interrupt (taint). taovf is interrupt level irq1, vector c2h. taint also belongs to interrupt level irq1, but is assigned the separate vector address, c0h. timer a overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. timer a match/capture interrupt, taint pending condition is also cleared by hardware when it has been serviced. interval timer function the timer a module can generate an interrupt: the timer a match interrupt (taint). taint belongs to interrupt level irq1, and is assigned the separate vector address, c0h. when the timer a match interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. in interval timer mode, a match signal is generated and taout is toggled when the counter value is identical to the value written to the timer a reference data register, tadata. the match signal generates a timer a match interrupt (taint, vector c0h) and clears the counter. if, for example, you write the value 10h to tadata and 0ah to tacon, the counter will increment until it reaches 10h. at this point, the timer a interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the taout pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer a data register, tadata. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ffh, and then continues incrementing from 00h. although you can use the match signal to generate a timer a overflow interrupt, interrupts are not typically used in pwm-type applications. instead, the pulse at the taout pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk ? 256. capture mode in capture mode, a signal edge that is detected at the tacap pin opens a gate and loads the current counter value into the timer a data register. you can select rising or falling edges to trigger this operation. timer a also gives you capture-input source: the signal edge at the tacap pin. you select the capture input by setting the value of the timer a capture input selection bit in the port 0 control register, p0conh, (set 1, bank 0, e6h). when p0conh.1-.0 is ?00? or ?01?, the tacap input or normal input is selected. when p0conh.1-.0 is set to 1x, normal push-pull output is selected. both kinds of timer a interrupts can be used in capture mode: the timer a overflow interrupt is generated whenever a counter overflow occurs; the timer a match/capture interrupt is generated whenever the counter value is loaded into the timer a data register. by reading the captured data value in tadata, and assuming a specific value for the timer a clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the tacap pin.
S3C84H5/f84h5 8-bit timer a/b 11-3 timer a control register (tacon) you use the timer a control register, tacon, to: ? select the timer a operating mode (interval timer, capture mode and pwm mode) ? select the timer a input clock frequency ? clear the timer a counter, tacnt ? enable the timer a overflow interrupt or timer a match/capture interrupt ? clear timer a match/capture interrupt pending conditions tacon is located in set 1, bank 1 at address e1h, and is read/write addressable using register addressing mode. a reset clears tacon to '00h'. this sets timer a to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer a interrupts. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. the timer a overflow interrupt (taovf) is interrupt level irq1 and has the vector address c2h. when a timer a overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer a match/capture interrupt (irq1, vector c0h), you must write tacon.1 to "1". to generate the exact time interval, you should write tacon.3 and .0 to ?1?, which cleared counter and interrupt pending bit. when interrupt service routine is served, the pending condition must be cleared by software by writing a ?0? to the interrupt pending bit (tintpnd.0 or tintpnd.1). . timer a control register (tacon) 00 = interval mode (taout mode) e1h, set 1, bank 1, r/w, reset: 00h lsb msb.7.6.5.4.3.2.1.0 timer a match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrrupt timer a input clock selection bit: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = external clock (tack) timer a operating mode selection bit: 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt and match interrupt can occur) timer a start/stop bit: 0 = stop timer a 1 = start timer a timer a overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrrupt timer a counter clear bit: 0 = no effect 1 = clear the timer a counter ( when write ) note: when th counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically. figure 11-1. timer a cont rol register (tacon)
8-bit timer a/b S3C84H5/f84h5 11-4 block diagram notes: 1. when pwm mode, match signal cannot clear counter. 2. pending bit is located at tintpnd register. clear match tacon.7-.6 f xx/1024 f xx/256 f xx/64 tack tacon.2 pending tacon.3 overflow taovf tacap taout(tapwm) tintpnd.0 tacon.5.-4 data bus 8 data bus 8 m u x m u x 8-bit up-counter (read only) 8-bit comparator timer a buffer reg timer a data register (read/write) m u x tacon.1 pending taint tintpnd.1 tacon.0 tacon.5.4 m u x figure 11-2. timer a fu nctional bloc k diagram
S3C84H5/f84h5 8-bit timer a/b 11-5 8-bit timer b overview the S3C84H5/f84h5 micro-controller has an 8-bit timer called timer b. timer b, which can be used to generate the carrier frequency of a remote controller signal. also, it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200hz to 20khz. these various frequencies can be used to generate a melody sound. timer b has two functions: ? as a normal interval timer, generating a timer b interrupt at programmed time intervals. ? to generate a programmable carrier pulse for a remote control signal at p1.0. block diagram data bus 8 tbcon.6-.7 f xx/4 note: in case of setting tbcon.5-.4 at '10', the value of the tbdatal register is loaded into the 8-bit counter when the operation of the timer b starts. and then if a underflow occurs in the counter, the value of the tbdatah register is loaded into the value of the 8-bit counter. however, if the next borrow occurs, the value of the tbdatal register is loaded into the value of the 8-bit counter. to output tbpwm as carrier wave, you have to set p4conl.7-.6 as "11". m u x f xx/8 fxx/64 fxx/256 tbcon.2 clk 8-bit down counter mux timer b data low byte register timer b data high byte register repeat control tbcon.0 t-ff tbcon.4-.5 tbcon.3 pg trigger signal tb underflow (tbuf) tbpwm(p1.4) tbint tbcon.1 data bus 8 figure 11-3. timer b func tional block diagram
8-bit timer a/b S3C84H5/f84h5 11-6 timer b control register (tbcon) timer b control register (tbcon) d0h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 timer b mode selection bit: 0 = one-shot mode 1 = repeating mode timer b input clock selection bit: 00 = fxx/4 01 = fxx/8 10 = fxx/64 11 = fxx/256 timer b interrupt time selection bit: 00 = elapsed time for low data value 01 = elapsed time for high data value 10 = elapsed time for low and high data value 11 = invaild setting timer b start/stop bit: 0 = stop timer b 1 = start timer b timer b interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer b output flip-flop control bit: 0 = t-ff is low 1 = t-ff is high figure 11-4. timer b cont rol register (tbcon) timer b data high-byte register (tbdatah) d1h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 reset value: ffh timer b data low-byte register (tbdatal) d2h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 reset value: ffh figure 11-5. timer b data registers (tbdatah, tbdatal)
S3C84H5/f84h5 8-bit timer a/b 11-7 timer b pulse width calculations t low t low t high to generate the above repeated waveform consisted of low period time, t low , and high period time, t high . when t-ff = 0, t low = (tbdatal + 1) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. t high = (tbdatah + 1) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. when t-ff = 1, t low = (tbdatah + 1) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. t high = (tbdatal + 1) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. to make t low = 24 us and t high = 15 us. f osc = 4 mhz, fx = 4 mhz/4 = 1 mhz when t-ff = 0, t low = 24 us = (tbdatal + 1) /fx = (tbdatal + 1) x 1us, tbdatal = 23. t high = 15 us = (tbdatah + 1) /fx = (tbdatah + 1) x 1us, tbdatah = 14. when t-ff = 1, t high = 15 us = (tbdatal + 1) /fx = (tbdatal + 1) x 1us, tbdatal = 14. t low = 24 us = (tbdatah + 1) /fx = (tbdatah + 1) x 1us, tbdatah = 23.
8-bit timer a/b S3C84H5/f84h5 11-8 timer b clock 0h t-ff = '0' tbdatal = 01-ffh tbdatah = 00h t-ff = '0' tbdatal = 00h tbdatah = 01-ffh t-ff = '0' tbdatal = 00h tbdatah = 00h t-ff = '1' tbdatal = 00h tbdatah = 00h high low low high timer b clock t-ff = '1' tbdatal = dfh tbdatah = 1fh t-ff = '0' tbdatal = dfh tbdatah = 1fh t-ff = '1' tbdatal = 7fh tbdatah = 7fh t-ff = '0' tbdatal = 7fh tbdatah = 7fh 0h 100h 200h e0h 20h 20h e0h 80h 80h 80h 80h figure 11-6. timer b output flip flop waveforms in repeat mode
S3C84H5/f84h5 8-bit timer a/b 11-9 programming tip ? to generate 38 khz, 1/3duty signal through p2.0 this example sets timer b to the repeat mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 38 khz, 1/3 duty carrier frequency. the program parameters are: 17.59 s 37.9 khz 1/3 duty 8.795 s ? timer b is used in repeat mode ? oscillation frequenc y is 16 mhz (0.0625 s), fx=fxx/4=4mhz (0.25 s) ? tbdatah = 8.795 s/0.25 s = 35.18, tbdatal = 17.59 s/0.25 s = 70.36 ? set p4.3 to tbpwm mode. org 0100h ; reset address start di sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ? ? ld tbdatal,#(35-1) ; set 17.5 s ld tbdatah,#(70-1) ; set 8.75 s ld tbcon,#00100111b ; clock source fxx/4 ; disable timer b interrupt. ; select repeat mode for timer b. ; start timer b operation. ; set timer b output flip-flop (t-ff) high. ; ld p1conlh,#0c0h ; set p1.4 to tbpwm mode. ; this command generates 38 khz, 1/3 duty pulse signal through p1.4. ? ? ? note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
8-bit timer a/b S3C84H5/f84h5 11-10 programming tip ? to generate a one pulse signal through p2.0 this example sets timer b to the one shot mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 40 s width pulse. the program parameters are: 40 s ? timer b is used in one shot mode ? oscillation frequency is 4 mhz (fx=1/4 clock = 1 s) ? tbdatah = 40 s / 1 s = 40, tbdatal = 1 ? set p2.0 to tbpwm mode org 0100h ; reset address start di sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ? ? ld tbdatah,# (40-1) ; set 40 s ld tbdatal,# 1 ; set any value except 00h ld tbcon,#00010001b ; clock source fxx/4 ; disable timer b interrupt. ; select one shot mode for timer b. ; stop timer b operation. ; set timer b output flip-flop (t-ff) high ld p2conl,#03h ; set p2.0 to tbpwm mode. ? ? pulse_out: ld tbcon,#00000101b ; start timer b operation ; to make the pulse at this point. ? ; after the instruction is executed, 0.75 s is required ? ; before the falling edge of the pulse starts. ? note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 8-bit timer a/b 11-11 programming tip ? using the timer a org 0000h vector 0c0h,tamc_int vector 0c2h,taov_int org 0100h initial: di sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ld sph,#00000000b ; set stack area ld spl,#00000000b ld btcon,#10100011b ; disable watch-dog ld p1conl,#0abh ; enable taout output sb1 ld tadata,#80h ld tacon,#01001010b ; match interrupt enable ; 6.55 ms duration (10 mhz x?tal) sb0 ei main: ? main routine ? jr t,main tamc_int: ? interrupt service routine ? iret taov_int: interrupt service routine iret .end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
8-bit timer a/b S3C84H5/f84h5 11-12 programming tip ? using the timer b org 0000h vector 0beh,tbun_int org 0100h initial: di sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ld imr,#00000001b ; enable irq0 interrupt ld sph,#00000000b ; set stack area ld spl,#00000000b ld btcon,#10100011b ; disable watch-dog ld p2conl,#03h ; enable tbpwm output ld tbdatah,#80h ld tbdatal,#80h ld tbcon,#11101110b ; enable interrupt, fxx/256, repeat ; duration 6.605ms (10 mhz x?tal) ei main: ? main routine ? jr t,main tbun_int: ? interrupt service routine ? iret .end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 16-bit timer 1(0,1) 12-1 12 16-bit timer 1(0,1) overview the S3C84H5/f84h5 has two 16-bit timer/counters. the 16-bit timer 1(0,1) is an 16-bit general-purpose timer/counter. timer 1(0,1) has three operating modes, one of which you select using the appropriate t1con0, t1con1 setting is ? interval timer mode (toggle output at t1out0, t1out1 pin) ? capture input mode wi th a rising or falling edge trig ger at the t1cap0, t1cap1 pin ? pwm mode (t1pwm0, t1pwm1); pwm output shares their output port with t1out0, t1out1 pin timer 1(0,1) has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, 64, 8, 1) with multiplexer ? external clock input pin (t1ck0, t1ck1) ? a 16-bit counter (t1cnth0/l0, t1cnth1/l1), a 16-bit comparator, and two 16-bit reference data register (t1datah0/l0, t1datah1/l1) ? i/o pins for capture input (t1cap0, t1cap1), or match output (t1out0, t1out1) ? timer 1(0) overflow interrupt (irq2, vector c6h) and match/capture interrupt (irq2, vector c4h) generation ? timer 1(1) overflow interrupt (irq2, vector cah) and match/capture interrupt (irq2, vector c8h) generation ? timer 1(0) control register, t1con0 (set 1, e8h, bank 1, read/write) ? timer 1(1) control register, t1con1 (set 1, e9h, bank 1, read/write)
16-bit timer 1(0,1) S3C84H5/f84h5 12-2 function description timer 1(0,1) interrupts (irq2, vectors c4h, c6h, c8h and cah) the timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (t1ovf0), and the timer 1(0) match/capture interrupt (t1int0). t1ovf0 is interrupt level irq2, vector c6h. t1int0 also belongs to interrupt level irq2, but is assigned the separate vector address, c4h. a timer 1(0) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer 1(0) match/capture interrupt, t1int0 pending condition is also cleared by hardware when it has been serviced. the timer 1(1) module can generate two interrupts, the timer 1(1) overflow interrupt (t1ovf1), and the timer 1(1) match/capture interrupt (t1int1). t1ovf1 is interrupt level irq2, vector cah. t1int1 also belongs to interrupt level irq2, but is assigned the separate vector address, c8h. a timer 1(1) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer 1(1) match/capture interrupt, t1int1 pending condition is also cleared by hardware when it has been serviced. interval mode (match) the timer 1(0) module can generate an interrupt: the timer 1(0) match interrupt (t1int0). t1int0 belongs to interrupt level irq2, and is assigned the separate vector address, c4h. in interval timer mode, a match signal is generated and t1out0 is toggled when the counter value is identical to the value written to the timer 1 reference data registers, t1datah0 and t1datal0. the match signal generates a timer 1(0) match interrupt (t1int0, vector c4h) and clears the counter value. the timer 1(1) module can generate an interrupt: the timer 1(1) match interrupt (t1int1). t1int1 belongs to interrupt level irq2, and is assigned the separate vector address, c8h. in interval timer mode, a match signal is generated and t1out1 is toggled when the counter value is identical to the value written to the timer 1 reference data register, t1datah1 and t1datal1. the match signal generates a timer 1(1) match interrupt (t1int1, vector c8h) and clears the counter value. capture mode in capture mode for timer 1(0), a signal edge that is detected at the t1cap0 pin opens a gate and loads the current counter value into the timer 1 data registers (t1datah0, t1datal0 fo r rising edge, or falling edge). you can select rising or falling ed ge to trigger this op eration. the timer 1(0) also gives you capt ure input source, the signal edge at the t1cap0 pin. you select the capture input by setting the value of the timer 1(0) capture input selection bit in the port 0 control register high, p0conh, (set 1 bank0, e6h). both kinds of timer 1(0) interrupts (t1ovf0, t1int0) can be used in capture mode, the timer 1(0) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(0) capture interrupt is generated whenever the counter value is loaded into the timer 1 data register. by reading the captured data value in t1datah0, t1datal0, and assuming a specific value for the timer 1(0) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t1cap0 pin. in capture mode for timer 1(1), a signal edge that is detected at the t1cap1 pin opens a gate and loads the current counter value into the timer 1 data register (t1datah1, t1datal1 fo r rising edge, or falling edge). you can select rising or falling edges to tr igger this operation. the timer 1(1) also gives you capture input source, the signal edge at the t1cap1 pin. you select the capture input by setting the value of the timer 1(1) capture input selection bit in the port 0 control register low, p0conl, (set 1 bank0, e7h). both kinds of timer 1(1) interrupts (t1ovf1, t1int1) can be used in capture mode, the timer 1(1) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(1) capture interrupt is generated whenever the counter value is loaded into the timer 1 data register. by reading the captured data value in t1datah1, t1datal1, and assuming a specific value for the timer 1(1) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t1cap1 pin.
S3C84H5/f84h5 16-bit timer 1(0,1) 12-3 pwm mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t1out0, t1out1 pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0,1) data registers. in pwm mode, however, the match signal does not clear the counter but can generate a match in terrupt. inst ead, it runs cont inuously, overflowing at ffffh, and then continuous increasing from 0000h. whenever an overflow occur, an overflow (t1ovf0,1) interrupt can be generated. although you can use the match or overflow interrupts in the pwm mode, these interrupts are not typically used in pwm-type applications. instead, the pulse at the t1out0, t1out1 pin is held to low level as long as the reference data value is less than or equal to( ) the counter value and then the pulse is held to high level for as long as the data value is greater than( > ) the counter value. one pulse width is equal to t clk timer 1(0,1) control register (t1con0, t1con1) you use the timer 1(0,1) control register, t1con0, t1con1, to: ? select the timer 1(0,1) operating mode (interval timer, capture mode, pwm mode) ? select the timer 1(0,1) input clock frequency ? clear the timer 1(0,1) counter, t1cnth0/l0, t1cnth1/l1 ? enable the timer 1(0,1) overflow interrupt ? enable the timer 1(0,1) match/capture interrupt t1con0 is located in set 1 and bank 1 at address e8h, and is read/write addressable using register addressing mode. t1con1 is located in set 1 and bank 1 at address e9h, and is read/write addressable using register addressing mode. a reset clears t1con0, t1con1 to ?00h?. this sets timer 1(0,1) to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1(0,1) interrupts. to disable the counter operation, please set t1con(0,1).7-.5 to 111b. you can clear the timer 1(0,1) counter at any time during normal operation by writing a ?1? to t1con(0,1).3. the timer 1(0) overflow interrupt (t1ovf0) is interrupt level irq2 and has the vector address c6h. and, the timer 1(1) overflow interrupt (t1ovf1) is interrupt level irq2 and has the vector address cah. to generate the exact time interval, you should write ?1? to t1con(0,1).2 and clear appropriate pending bits of the tintpnd register. to detect a match/capture or overflow interrupt pending condition when t1int0, t1int1 or t1ovf0, t1ovf1 is disabled, the application program should poll the pending bit tintpnd register, bank 1, address e0h. when a ?1? is detected, a timer 1(0,1) match/capture or overflow interrupt is pending. when the sub-routine has been serviced, the pending condition must be cleared by software by writing a ?0? to the interrupt pending bit. if interrupts (match/capture or overflow) are enabled, the pending bit is cleared automatically by hardware.
16-bit timer 1(0,1) S3C84H5/f84h5 12-4 note: interrupt pending bits are located in tintpnd register. timer 1 control registe r (t1con0) e8h, set 1, bank 1, r/w (t1con1) e9h, set 1, bank 1, r/w lsb msb.7.6.5.4.3.2.1.0 timer 1 overflow interrupt enable bit 0 = disable overflow interrupt 1 = enable overflow interrrupt timer 1 clock source selection bit: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx 101 = external clock fa lling edge 110 = external clock rising edge 111 = counter stop timer 1 operating mode selection bit: 00 = interval mode 01 = capture mode (capture on rising edge, ovf can occur) 10 = capture mode (capture on falling edge, ovf can occur) 11 = pwm mode timer 1 match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrrupt timer 1 counter clear bit: 0 = no effect 1 = clear counter (auto-clear bit) figure 12-1. timer 1(0,1) control register (t1con0, t1con1)
S3C84H5/f84h5 16-bit timer 1(0,1) 12-5 timer a, timer 1 pending register (tintpnd) e0h, set 1, bank 1, r/w lsb msb.7.6.5.4.3.2.1.0 timer a overflow interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending not used (must keep always 0) timer a match/capture interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending timer 1(0) overflow interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending timer 1(0) match/capture interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending timer 1(1) overflow interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending timer 1(1) match/capture interrupt pending bit 0 = no interrupt pending 1 = interrrupt pending figure 12-2. timer a, timer 1(0, 1) pending register (tintpnd)
16-bit timer 1(0,1) S3C84H5/f84h5 12-6 block diagram f xx/1 f xx/64 fxx/8 v ss t1ck f xx/256 f xx/1024 notes: 1. when pwm mode, match signal cannot clear counter. 2. pending bit is located at tintpnd register. clear match t1con.7-.5 t1con.0 pending t1con.2 overflow t1ovf t1cap t1out(t1pwm) tintpnd t1con.4.3 t1con.4-.3 data bus 8 data bus 8 m u x m u x 16-bit up-counter (read only) 16-bit comparator 16-bit timer buffer 16-bit timer data register (t1datah/l) m u x t1con.1 pending t1int tintpnd m u x figure 12-3. timer 1(0,1) functional block diagram
S3C84H5/f84h5 16-bit timer 1(0,1) 12-7 programming tip ? us ing the timer 1(0) org 0000h vector 0c4h,tim1_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ld imr,#00001000b ; enable irq2 interrupt ld sph,#00000000b ; set stack area ld spl,#00000000b ld btcon,#10100011b ; disable watch-dog sb1 ld t1con0,#01000110b ; enable interrupt ,fxx/64, interval, ; interval= 1.536 ms (10 mhz x?tal) ldw t1datah0,#00f0h ; t1 datah0=00h, t1datal0=f0h sb0 ei main: ? main routine ? jr t,mian tim1_int: ? ? interrupt service routine ? ? iret end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 10-bit pwm (pulse width modulation) 13-1 13 10-bit pwm (pulse width modulation) overview this microcontroller has the 10-bit pwm circuit. the operation of all pwm circuit is controlled by a single control register, pwmcon. the pwm counter is a 10-bit incrementing counter. it is used by the 10-bit pwm circuits. to start the counter and enable the pwm circuits, you set pwmcon.2 to "1". if the counter is stopped, it retains its current count value; when re-started, it resumes counting from the retained count value. when there is a need to clear the counter you set pwmcon.3 to "1". you can select a clock for the pwm counter by set pwmcon.6?.7. clocks which you can select are f osc /64, f osc /8, f osc /2, f osc /1. function description pwm the 10-bit pwm circuits have the following components: ? 8-bit comparator and extension cycle circuit ? 8-bit reference data register (pwmdatah .7?.0) ? 2-bit extension data register (pwmdatal .1?.0) ? pwm output pins (p2.1/pwm) pwm counter to determine the pwm module's base operating frequency, the upper 8-bits of counter is compared to the pwm data (pwmdatah .7?.0). in order to achieve higher resolutions, the lower 2-bits of the pwmdatal counter can be used to modulate the "stretch" cycle. to control the "stretching" of the pwm output duty cycle at specific intervals, the lower 2-bits of pwmdatal counter value is compared with the pwmdatal .1?.0.
10-bit pwm (pulse width modulation) S3C84H5/f84h5 13-2 pwm data and exte nsion registers pwm (duty) data registers located in set 1, bank1 at address f3h-f4h, determine the output value generated by each 10-bit pwm circuit. to program the required pwm output, you load the appropriate initialization values into the 8-bit reference data register (pwmdatah .7?.0) and the 2-bit extension data register (pwmdatal .1?.0). to start the pwm counter, or to resume counting, you set pwmcon.2 to "1". a reset operation disables all pwm output. the current counter value is retained when the counter stops. when the counter starts, counting resumes at the retained value. pwm clock rate the timing characteristics of pwm output is based on the f osc clock frequency. the pwm counter clock value is determined by the setting of pwmcon.6?.7. table 13-1. pwm contro l and data registers register name mnemonic address function pwm data registers pwmdatah .7?.0 f3h, set 1 bank 1 8-bit pwm basic cycle frame value pwmdatal .1?.0 f4h, set 1 bank 1 2-bit extension ("stretch") value pwm control registers pwmcon f5h, set 1 bank 1 pwm counter stop/start (resume), and pwm counter clock settings pwm function description the pwm output signal toggles to low level whenever the 8-bit counter matches the reference data register (pwmdatah). if the value in the pwmdatah register is not zero, an overflow of the 8-bits of counter causes the pwm output to toggle to high level. in this way, the reference value written to the reference data register determines the module's base duty cycle. the value in the lower 2-bits of pwmdatal counter is compared with the extension settings in the 2-bit extension data register (pwmdatal .1?.0). this lower 2-bits of counter value, together with extension logic and the pwm module's extension data register , is then used to "stretch" the duty cycle of the pwm output. the "stretch" value is one extra clock period at specific intervals, or cycles (see table 12-2). if, for example, the value in the extension pwmdatah register is '00b' and pwmdatal register is ?01b?, the 2nd cycle will be one pulse longer than the ot her 3 cycles. if the base duty cycle is 50 %, the du ty of the 2nd cycle will therefore be "stretched" to approximately 51% duty. for example, if you write 10b to the extension data register, all odd-numbered pulses will be one cycle longer. if you write 11h to the extension data register, all pulses will be stretched by one cycle except the 4th pulse. pwm output goes to an output buffer and then to the corresponding pwm output pin. in this way, you can obtain high output resolution at high frequencies.
S3C84H5/f84h5 10-bit pwm (pulse width modulation) 13-3 table 13-2. pwm output "stretch " values for extension data register (pwmdatal .1?.0) pwmdatal bit (bit1?bit0) "stretched" cycle number 00 ? 01 2 10 1, 3 11 1, 2, 3 250 ns 250 ns 8 ms 8 ms 250 ns 0h 100h 200h 4 mhz 00000000b xxxxxx00b 00000001b xxxxxx00b 10000000b xxxxxx00b 11111111b xxxxxx00b pwm clock: register values: (pwmdatah pwmdatal) pwm data figure 13-1. 10-bit pwm basic waveform
10-bit pwm (pulse width modulation) S3C84H5/f84h5 13-4 1st 2nd 3th 4th 1st 2nd 3th 4th 500 ns 750 ns 0h 40h 4 mhz 0h 40h pwm clock: 4 mhz 00000010b xxxxxx01b pwmdata : 00001001b : xxxxxx01 b basic waveform extended waveform figure 13-2. 10-bit extended pwm waveform
S3C84H5/f84h5 10-bit pwm (pulse width modulation) 13-5 pwm control register (pwmcon) the control register for the pwm module, pwmcon, is located at register address f5h. pwmcon is used the 10-bit pwm modules. bit settings in the pwmcon register control the following functions: ? pwm counter clock selection ? pwm data reload interval selection ? pwm counter clear ? pwm counter stop/start (or resume) operation ? pwm counter overflow (10-bit counter overflow) interrupt control a reset clears all pwmcon bits to logic zero, disabling the entire pwm module. .7 .6 .5 .4 .3 .2 .1 .0 lsb msb pwm control register (pwmcon) f5h, r/w, reset: 00h pwm input clock selection bits: 00 = f osc /64 01 = f osc /8 10 = f osc /2 11 = f osc /1 pwm counter clear bit: 0 = no effect 1 = clear the pwm counter pwm counter enable bit: 0 = stop counter 1 = start (resume countering) pwm ovf interrupt enable bit: 0 = disable interrupt 1 = enable interrupt pwm ovf interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt pending not used for S3C84H5/f84h5 pwmdata reload interval selection bit: 0 = reload from 10bit up counter overflow 1 = reload from 8bit up counter overflow figure 13-3. pwm control register (pwmcon)
10-bit pwm (pulse width modulation) S3C84H5/f84h5 13-6 8-bit comparator "1" when reg > count "1" when reg = count extension control logic extension data buffer 2-bit extend bit (pwmdatal) 8-bit up counter (pwmdatah) 8-bit data buffer 8-bit data register (f3h) pwmcon.3 (clear) 8 bit up counter overflow data bus (7:0) f3h, set1 bank1 pwmdatah p2.1/pwm 2-bit counter 8-bit counter pwmcon.2 mux f osc /64 f osc f osc /8 f osc /2 pwmcon.6-.7 set1 bank1, f4h pwmdatal(.1-.0) figure 13-4. pwm functional block diagram
S3C84H5/f84h5 10-bit pwm (pulse width modulation) 13-7 ) programming tip ? programming the pw m module to sample specifications ;--------------<< interrupt vector address >> org 0000h vector 0dah,int_pwm ;--------------<< initialize system and peripherals >> org 0100h reset: di ; disable interrupt sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ld btcon,#10100011b ; watchdog disable ? ? ld p2conl,#00001100b ; configure p2.1 pwm output ld pwmcon,#00000110b ; f osc /64, counter/interrupt enable ld pwmdatah,,#80h ld pwmdatal,#0 ei ; enable interrupt ;--------------<< main loop >> main: ? ? jr t,main ;--------------<< interrupt service routines >> int_pwm: ; pwm interrupt service routine ? and pwmcon,#11111110b ; pending bit clear iret ? end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 serial i/o interface 14-1 14 serial i/o interface overview serial i/o module, sio can interface with various types of external devices that require serial data transfer. the components of each sio function block are: ? 8-bit control register (siocon) ? clock selection logic ? 8-bit data buffer (siodata) ? 8-bit presale (siops) ? 3-bit serial clock counter ? serial data i/o pins (si, so) ? external clock input pin (sck) sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio module, follow these basic steps: 1. configure the i/o pins at port 2 (so, sck, si) by loading the appropriate value to the p2conl/h register. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit (siocon.1) to "1". 4. when you the transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (siocon.0) is set to "1" and an sio interrupt request is generated.
serial i/o interface S3C84H5/f84h5 14-2 serial i/o control registers (siocon) the control registers for serial i/o interface, siocon, is located in set1, bank 1 at f2h. it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to "00h". this configures the corresponding module with an internal clock source at the sck, selects receive-only operating mode, and clears the 3-bit counter. the data shift operation and the interrupt are disabled. the selected data direction is msb-first. lsb msb sio control registers(siocon) f2h, set 1, bank 1,r/w, reset: 00h siointerrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending .7 .6 .5 .4 .3 .2 .1 .0 sio shift clock select bit: 0 = internal clock (p.s clock) 1 = external clock (sck) data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shfter and clock counter sio mode selction bit: 0 = rececive-only mode 1 = transmit/receive mode shift clock edge selction bit: 0 = tx falling edges, rx at rising edges 1 = tx rising edges, rx at falling edges figure 14-1. serial i/o interfac e control register (siocon)
S3C84H5/f84h5 serial i/o interface 14-3 sio prescaler register (siops) the control register for serial i/o interface module, siops is located in set 1, bank 1 at f0h. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock(xin/4) / (siop+ 1), or external sck input clock sio pre-scaler registers (siops) f0h, set1, bank1, r/w msb lsb .5 .4 .1 .0 .7 .6 .3 .2 baud rate = (xin/4)/(siops+1) figure 14-2. sio pre-scaler register (siops) sio int pending 3-bit counter siocon.0 mux 8-bit sio shift buffer (siodata) 8-bit prescaler 1/2 x in /2 siops(f4h) sck siocon.7 (shift clock source select) toggle prescaler value = 1/(siops + 1) clear clk siocon.1 (interrupt enable) clk si siocon.3 siocon.4 (edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so figure 14-3. sio funct ional block diagram
serial i/o interface S3C84H5/f84h5 14-4 so transmit complete irqs set siocon.3 do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 si sck figure 14-4. serial i/o timing in transmi t-receive mode (tx at falling, siocon.4 = 0) irqs do7 do6 do5 do4 do3 do2 do1 do0 d17 d16 d15 d14 d13 d12 d11 d10 sck transmit complete set siocon.3 si so figure 14-5. serial i/o timing in transmit-rec eive mode (tx at rising, siocon.4 = 1)
S3C84H5/f84h5 serial i/o interface 14-5 data output transmit complete irq5 start d7 d6 d5 d4 d3 d2 d1 d0 data input shift clock high impedance figure 14-6. serial i/o timi ng in receive-only mode programming tip ? sio org 0000h vector 00h, int_sio org 0100h initial: di sb1 ; extra command only for debugging (1) ld 0f7h,#5fh ; extra command only for debugging (1) sb0 ; extra command only for debugging (1) ld btcon, #10100010b ; watch-dog disable ld clkcon, #00011000b ; non-divided cpu clock ld spl, #00h ; ? ? ld p2conh, #10101111b ; sio setting ld p2conl, #00101010b ? ? ld siocon, #00100110b ; enable sio/interrupt ld siops, #20 ; setting baud rate ? ? ei
serial i/o interface S3C84H5/f84h5 14-6 programming tip ? sio (continued) main: ? ? ? call sub_sio ; data transmit routine ? ? ? jp main sub_sio: ld siodata, transbuf ; 1-byte transmission or siocon, #00001000b ; shift start (8-bit transmit) ? ? ret int_sio: and siocon, #11111110 ; pending bit clear ? ? ? iret note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 uart 14-1 15 uart overview the uart block has a full-duplex serial port with programmable operating modes: there is one synchronous mode and three uart (universal asynchronous receiver/transmitter) modes: ? shift register i/o with baud rate of fxx/(16 (16bit brdata+1)) ? 8-bit uart mode; variable baud rate, fxx/(16 (16bit brdata+1)) ? 9-bit uart mode; variable baud rate, fxx/(16 (16bit brdata+1)) uart receive and transmit buffers are both accessed via the data register, udata, is at address f5h. writing to the uart data register loads the transmit buffer; reading the uart data register accesses a physically separate receive buffer. when accessing a receive data buffer (shift register), reception of the next byte can begin before the previously received byte has been read from the receive register. however, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost (overrun error). in all operating modes, transmission is started when any instruction (usually a write operation) uses the udata register as its destination address. in mode 0, serial data reception starts when the receive interrupt pending bit (uartpnd.1) is "0" and the receive enable bit (uartcon.4) is "1". in mode 1 and 2, reception starts whenever an incoming start bit ("0") is received and the receive enable bit (uartcon.4) is set to "1". programming procedure to program the uart modules, follow these basic steps: 1. configure p2.6 and p2.7 to alternative function (rxd (p2.6), txd (p2.7)) for uart module by setting the p1conh register to appropriatly value. 2. load an 8-bit value to the uartcon control register to properly configure the uart i/o module. 3. for parity generation and check in uart mode 2, set parity enable bit (uartpnd.5) to ?1?. 4. for interrupt generation, set the uart interrupt enable bit (uartcon.1 or uartcon.0) to "1". 5. when you transmit data to the uart buffer, write transmit data to udata, the shift operation starts. 6. when the shift operation (transmit/receive) is completed, uart pending bit (uartpnd.1 or uartpnd.0) is set to "1" and an uart interrupt request is generated.
uart S3C84H5/f84h5 15-2 uart control register (uartcon) the control register for the uart is called uartcon at address f6h. it has the following control functions: ? operating mode and baud rate selection ? multiprocessor communication and interrupt control ? serial receive enable/disable control ? 9th data bit location for transmit and receive operations (mode 2) ? parity generation and check for transmit and receive operations (mode 2) ? uart transmit and receive interrupt control a reset clears the uartcon value to "00h". so, if you want to use uart module, you must write appropriate value to uartcon.
S3C84H5/f84h5 uart 14-3 if parity disable mode (pen = 0), location of the 9th data bit that was received in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for receive data in uart mode 2. 0 : even parity check for the received data 1 : odd parity check for the received data uart control register (uartcon) f6h, set1, bank 0, r/w, reset value: 00h ms1 msb lsb received interrupt enable bit: 0 = disable 1 = enable transmit interrupt enable bit: 0 = disable 1 = enable serial data receive enable bit: 0 = disable 1 = enable multiprocessor communication (1) enable bit (mode 2 only): 0 = disable 1 = enable if parity disable mode (pen = 0), location of the 9th data bit to be transmitted in uart mode 2 ("0" or "1"). if parity enable mode (pen = 1), even/odd parity selection bit for transmit data in uart mode 2; 0 : even parity bit generation for transmit data 1 : odd parity bit generation for transmit data operating mode and baud rate selection bits (see table below) ms0 mce re tb8 rb8 rie tie ms1 ms0 0 0 1 0 1 x mode description (2) baud rate 0 1 2 shift register fxx / (16 x (16bit brdata + 1)) 8-bit uart fxx / (16 x (16bit brdata + 1)) 9-bit uart fxx / (16 x (16bit brdata + 1)) notes: 1. in mode 2, if the uartcon.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". in mode 1, if uartcon.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received. 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits for serial data receive and transmit. 3. parity enable bits, pen, is located in the uartpnd register at address f4h. 4. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. figure 15-1. uart control register (uartcon)
uart S3C84H5/f84h5 15-4 uart interrupt pending register (uartpnd) the uart interrupt pending register, uartpnd is located at address f4h. it contains the uart data transmit interrupt pending bit (uartpnd.0) and the receive interrupt pending bit (uartpnd.1). in mode 0 of the uart module, the receive interrupt pending flag uartpnd.1 is set to "1" when the 8th receive data bit has been shifted. in mode 1 or 2, the uartpnd.1 bit is set to "1" at the halfway point of the stop bit's shift time. when the cpu has acknowledged the receive interrupt pending condition, the uartpnd.1 flag must be cleared by software in the interrupt service routine. in mode 0 of the uart module, the transmit interrupt pending flag uartpnd.0 is set to "1" when the 8th transmit data bit has been shifted. in mode 1 or 2, the uartpnd.0 bit is set at the start of the stop bit. when the cpu has acknowledged the transmit interrupt pending condition, the uartpnd.0 flag must be cleared by software in the interrupt service routine. uart pending register (uartpnd) f4h, set1, bank 0, r/w, reset value: 00h msb lsb pen rpe rip tip .7 .6 .3 .2 uart parity enable/disable: 0 = disable 1 = enable uart receive parity error: 0 = no error 1 = parity error uart receive interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending uart transmit interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending not used (must keep always 0) not used (must keep always 0) notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. a "0" has no effect. 2. to avoid errors, we recommend using load instruction (except for ldb), when manipulating uartpnd values. 3. parity enable and parity error check can be available in 9-bit uart mode (mode 2) only. 4. parity error bit (rpe) will be refreshed wh enever 8th receive data bit has been shifted. figure 15-2. uart interrupt pending register (uartpnd)
S3C84H5/f84h5 uart 14-5 in mode 2 (9-bit uart data ), by setting the parity enable bit (pen) of uartpnd register to '1', the 9 th data bit of transmit data will be an automatically generated parity bit. also, the 9 th data bit of the receiv ed data will be treated as a parity bit for checking the received data. in parity enable mode (pen = 1), uartcon.3 (tb8) and uartcon.2 (rb8) will be a parity selection bit for transmit and receive data respectively. the uartcon.3 (tb8) is for settings of the even parity generation (tb8 = 0) or the odd parity generation (tb8 = 0) in the transmit mode. the uartcon.2 (rb8) is also for settings of the even parity checking (rb8= 0) or the odd parity checking (rb8 =1) in the receive mode. the parity enable (generation/checking) functions are not available in uart mode 0 and 1. if you don?t want to use a parity mode, uartcon.2 (rb8) and uartcon.3 (tb8) are a normal control bit as the 9 th data bit, in this case, pen must be disable (?0?) in mode 2. also it is needed to select the 9th data bit to be transmitted by writing tb8 to "0" or "1". the receive parity error flag (rpe) will be set to ?0? or ?1? dependin g on parity erro r whenever the 8 th data bit of the receive data has been shifted. uart data register (udata) uart data register (udata) f5h, set1, bank 0, r/w, reset value: ffh msb lsb .5 .4 .1 .0 .7 .6 .3 .2 transmit or receive data figure 15-3. uart data register (udata)
uart S3C84H5/f84h5 15-6 uart baud rate data register (brdatah, brdatal) the value stored in the uart baud rate register, (brdatah, brdatal), lets you determine the uart clock rate (baud rate). uart baud rate data register (brdatah) eeh, set1, bank 1, r/w, reset value: ffh (brdatal) efh, set1, bank 1, r/w, reset value: ffh .7 msb lsb .6 .5 .4 .3 .2 .1 .0 brud rate data figure 15-4. uart baud rate data register (brdatah, brdatal) baud rate calculations the baud rate is determined by the baud rate data register, 16bit brdata mode 0 baud rate = fxx/(16 (16bit brdata + 1)) mode 1 baud rate = fxx/(16 (16bit brdata + 1)) mode 2 baud rate = fxx/(16 (16bit brdata + 1))
S3C84H5/f84h5 uart 14-7 table 15-1. commonly used baud ra tes generated by 16bit brdata brdatah brdatal baud rate oscillation clock decimal hex decimal hex 230,400 hz 11.0592 mhz 0 0h 02 02h 115,200 hz 11.0592 mhz 0 0h 05 05h 57,600 hz 11.0592 mhz 0 0h 11 0bh 38,400 hz 11.0592 mhz 0 0h 17 11h 19,200 hz 11.0592 mhz 0 0h 35 23h 9,600 hz 11.0592 mhz 0 0h 71 47h 4,800 hz 11.0592 mhz 0 0h 143 8fh 76,800 hz 10 mhz 0 0h 7 7h 38,400 hz 10 mhz 0 0h 15 fh 19,200 hz 10 mhz 0 0h 31 1fh 9,600 hz 10 mhz 0 0h 64 40h 4,800 hz 10 mhz 0 0h 129 81h 2,400 hz 10 mhz 1 1h 3 3h 600 hz 10 mhz 4 4h 16 10h 38,461 hz 8 mhz 0 0h 12 0ch 12,500 hz 8 mhz 0 0h 39 27h 19,230 hz 4 mhz 0 0h 12 0ch 9,615 hz 4 mhz 0 0h 25 19h
uart S3C84H5/f84h5 15-8 block diagram zero detector udata rxd (p2.6) tie rie interrupt 1-to-0 transition detector re rie bit detector shift value ms0 ms1 ms0 ms1 rxd (p2.6) sam88 internal data bus write to udata baud rate generator s dq clk tb8 clk tx control start tx clock tip shift en send rx control rx clock start rip receive shift shift clock ms0 ms1 fxx sam88 internal data bus shift register udata 16 bit brdata txd (p2.7) txd (p2.7) figure 15-5. uart functional block diagram
S3C84H5/f84h5 uart 14-9 uart mode 0 function description in mode 0, uart is input and output through the rxd (p2.6) pin and txd (p2.7) pin outputs the shift clock. data is transmitted or received in 8-bit units only. the lsb of the 8-bit value is transmitted (or received) first. mode 0 transmit procedure 1. select mode 0 by setting uartcon.6 and .7 to "00b". 2. write transmission data to the shift register udata (f5h) to start the transmission operation. mode 0 receive procedure 1. select mode 0 by setting uatcon.6 and .7 to "00b". 2. clear the receive interrupt pending bit (uartpnd.1) by writing a "0" to uartpnd.1. 3. set the uart receive enable bit (uartcon.4) to "1". 4. the shift clock will now be output to the txd (p2.7) pi n and will read the data at the rxd (p2.6) pin. a uart receive interrupt (vector e4h) occurs when uartcon.1 is set to "1". transmit d0 d1 d2 d3 d4 d5 d6 d7 write to shift register (udata) rxd (data out) txd (shift clock) tip shift receive write to uartpnd (clear rip and set re) shift d0 d1 d2 d3 d4 d5 d6 d7 txd (shift clock) rxd (data in) re rip 12345678 figure 15-6. timing diagram for uart mode 0 operation
uart S3C84H5/f84h5 15-10 uart mode 1 function description in mode 1, 10-bits are transmitted (through the txd (p2.7) pin) or received (through the rxd (p2.6) pin). each data frame has three components: ? start bit ("0") ? 8 data bits (lsb first) ? stop bit ("1") when receiving, the stop bit is written to the rb8 bit in the uartcon register. the baud rate for mode 1 is variable. mode 1 transmit procedure 1. select the baud rate generated by 16bit brdata. 2. select mode 1 (8-bit uart) by setting uartcon bits 7 and 6 to '01b'. 3. write transmission data to the shift register udata (f5h). the start and stop bits are generated automatically by hardware. mode 1 receive procedure 1. select the baud rate to be generated by 16bit brdata. 2. select mode 1 and set the re (receive enable) bit in the uartcon register to "1". 3. the start bit low ("0") condition at the rxd (p1.4) pin will cause the ua rt module to start the serial data receive operation. transmit tip write to shift register (udata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift figure 15-7. timing diagram for uart mode 1 operation
S3C84H5/f84h5 uart 14-11 uart mode 2 function description in mode 2, 11-bits are transmitted (through the txd pin) or received (through the rxd pin). each data frame has four components: ? start bit ("0") ? 8 data bits (lsb first) ? programmable 9th data bit or parity bit ? stop bit ("1") < in parity disable mode (pen = 0) > the 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the tb8 bit (uartcon.3). when receiving, the 9th data bit that is received is wr itten to the rb8 bit (uartcon.2), while the stop bit is ignored. the baud rate for mode 2 is fosc/(16 x (16bit brdata + 1)) clock frequency. < in parity enable mode (pen = 1) > the 9th data bit to be transmitted can be an automatically generated parity of "0" or "1" depending on a parity generation by means of tb8 bit (uartcon.3). when receiving, the received 9th data bit is treated as a parity for checking receive data by means of the rb8 bit (uartcon.2), while the stop bit is ignored. the baud rate for mode 2 is fosc/(16 x (16bit brdata + 1)) clock frequency. mode 2 transmit procedure 1. select the baud rate generated by 16bit brdata. 2. select mode 2 (9-bit uart) by setting uartcon bits 6 and 7 to '10b'. also, select the 9th data bit to be transmitted by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?0? if you don?t use a parity mode. if you want to use the parity enable mode, select the parity bit to be transmitted by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?1?. 3. write transmission data to the shift register, udata (f5h), to start the transmit operation. mode 2 receive procedure 1. select the baud rate to be generated by 16bit brdata. 2. select mode 2 and set the receive enable bit (re) in the uartcon register to "1". 3. if you don?t use a parity mode, set pen bit of uartpnd register to ?0? to disable parity mode. if you want to use the parity enable mode, select the parity type to be check by writing tb8 to "0" or "1" and set pen bit of uartpnd register to ?1?. only 8 bits (bit0 to bit7) of received data are available for data value. 4. the receive operation starts when the signal at the rxd pin goes to low level.
uart S3C84H5/f84h5 15-12 transmit tip write to shift register (uartdata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift tb8 or parity bit rb8 or parity bit figure 15-8. timing diagram for uart mode 2 operation
S3C84H5/f84h5 uart 14-13 serial communication for multi processor configurations the s3c9-series multiprocessor communication features let a "master" S3C84H5/f84h5 send a multiple-frame serial message to a "slave" device in a multi- S3C84H5/f84h5 configuration. it does this without interrupting other slave devices that may be on the same serial line. this feature can be used only in uart mode 2 with the parity disable mode. in mode 2, 9 data bits are received. the 9th bit value is written to rb8 (uartcon.2). the data receive operation is concluded with a stop bit. you can program this function so that when the stop bit is re ceived, the serial in terrupt will be genera ted only if rb8 = "1". to enable this feature, you set the mce bit in the uartcon registers. when the mce bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. in this case, the 9th bit simply separates the address from the serial data. sample protocol for master/slave interaction when the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. note that in this case, an address byte differs from a data byte: in an address byte, the 9th bit is "1" and in a data byte, it is "0". the address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed. the addressed slave then clears its mce bit and prepares to receive incoming data bytes. the mce bits of slaves that were not addressed remain set, and they continue operating normally while ignoring the incoming data bytes. while the mce bit setting has no effect in mode 0, it can be used in mode 1 to check the validity of the stop bit. for mode 1 reception, if mce is "1", the receive in terrupt will be issu e unless a valid stop bit is received.
uart S3C84H5/f84h5 15-14 setup procedure for mult iprocessor communications follow these steps to configure multiprocessor communications: 1. set all S3C84H5/f84h5 devices (masters and slaves) to uart mode 2 with parity disable. 2. write the mce bit of all the slave devices to "1". 3. the master device's transmission protocol is: ? first byte: the address identifying the target slave device (9th bit = "1") ? next bytes: data (9th bit = "0") 4. when the target slave receives the first byte, all of the slaves are interrupted because the 9th data bit is "1". the targeted slave compares the address byte to its own address and then clears its mce bit in order to receive incoming data. the other slaves continue operating normally. full-duplex multi-S3C84H5/f84h5 interconnect . . . txd rxd master S3C84H5/ f84h5 txd rxd slave 1 txd rxd slave 2 txd rxd slave n S3C84H5/ f84h5 S3C84H5/ f84h5 S3C84H5/ f84h5 figure 15-9. connection exam ple for multiprocessor se rial data communications
S3C84H5/f84h5 a/d converter 16-1 16 a/d converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register, adcon (set 1, bank 0, f7h, read/write, but adcon.3 is read only) ? eight multiplexed analog data input pins (adc0?adc7) ? 10-bit a/d conversion data output register (addatah, addatal) function description to initiate an analog-to-digital conversion procedure, at first, you must configure p0.0?p0.3, p2.2?p2.3, p1.4? p1.5 to analog input before a/d conversions because the p0.0?p0.3, p2.2?p2.3, p1.4?p1.5 pins can be used alternatively as normal data i/o or analog input pins. to do this, you load the appropriate value to the p0conl, p2conl and p1conh (for adc0?adc7) register. and you write the channel selection data in the a/d converter control register adcon to select one of the eight analog input pins (adcn, n = 0?7) and set the conversion start or enable bit, adcon.0. a 10-bit conversion operation can be performed for only one analog input channel at a time. the read-write adcon register is located in set 1, bank 0 at address f7h. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adcon.6?.4) in the adcon register. to start the a/d conversion, you should set the enable bit, adcon.0. when a conversion is completed, adcon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addatah, addatal registers where it can be read. the adc module enters an idle state. remember to read the contents of addatah and addatal before anothe r conversion starts. other wise, the previous resu lt will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0?adc7 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result.
a/d converter S3C84H5/f84h5 16-2 a/d converter contro l register (adcon) the a/d converter control register, adcon, is located in set1, bank 0 at address f7h. adcon is read-write addressable using 8-bit instructions only. but, the eoc bit, adcon.3 is read only. adcon has four functions: ? bits 6?4 select an analog input pin (adc0?adc7). ? bit 3 indicates the end of conversion status of the a/d conversion. ? bits 2?1 select a conversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the eight analog input pins, adc0?adc7 by manipulating the 3-bit value for adcon.6?adcon.4 start or enable bit 0 = disable operation 1 = start operation a/d converter control register (adcon) f7h, set 1, bank 0, r/w (adcon.3 bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit (realy only): 0 = conversion not complete 1 = conversion complete a/d input pin selection bits: a/d input pin clock selection bit: .4 .5 000 001 010 011 100 101 110 111 adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 conversion clock .1 .2 0 1 0 1 0 0 1 1 fxx/16 fxx/8 fxx/4 not used .6 not used (must keep always 0) figure 16-1. a/d converter control register (adcon)
S3C84H5/f84h5 a/d converter 16-3 conversion data register high byte (addatah) f8h, set 1, bank 0, read only lsb msb.7.6.5.4.3.2.1.0 conversion data register low byte (addatal) f9h, set 1, bank 0, read only lsb msb x x x x x x .1 .0 figure 16-2. a/d converter data register (addatah, addatal) input pins adc0-adc7 (p0.0 - p0.3, p1.4 - p1.5, ) 10-bit result is loaded into a/d conversion data register to adcon.3 (eoc flag) avref avss analog comparator adcon.4-.6 (select one input pin of the assigned) adcon.0 (adc enable) adcon.0 (a/d conversion enable) adcon.2-.1 m u l t i p l e x e r + - clock selector successive approximation logic 10-bit d/a converter conversion result (addatah, addatal) to data bus fxx/16 fxx/8 fxx/4 p2.2 - p2.3 figure 16-3. a/d converter circuit diagram
a/d converter S3C84H5/f84h5 16-4 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref . conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks is required to complete a 10-bit conversion: with a 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/fxx). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 s at 10 mhz, 1 clock time = 4/fxx 50 adc clock adcon.0 1 . . . 40 clock previous value valid data set up time 10 clock addatah (8-bit) + addatal (2-bit) 9 8 7 6 5 4 3 2 1 0 conversion start eoc addata figure 16-4. a/d conver ter timing diagram
S3C84H5/f84h5 a/d converter 16-5 internal a/d conversion procedure 1. analog input must remain between the voltage range of av ss and av ref . 2. configure p0.0 ? p0.3, p1.4 ? p1.5, p2.2 ? p2.3 for analog input before a/d conversions. to do this, you load the appropriate value to the p0conl, p1conh and p2conl (for adc0?adc7) registers. 3. before the conversion operation starts, you must first select one of the eight input pins (adc0?adc7) by writing the appropriate value to the adcon register. 4. when conversion has been completed, (50 clocks have elapsed), the eoc, adcon.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah (8-bit) and addatal (2-bit), then the adc module enters an idle state. 6. the digital conversion result can now be read from the addatah and addatal register. reference voltage input analog input pin note: the symbol "r" signifies an offset resistor with a value of from 50 to 100 ? vss S3C84H5/ s3f84h5 adc0-adc7 avref r v dd v dd 104 101 avss figure 16-5. recommended a/d converter circuit for highest absolute accuracy
a/d converter S3C84H5/f84h5 16-6 programming tip ? configuring a/d converter ? sb1 ; extra command only for debugging (note) ld 0f7h,#5fh ; extra command only for debugging (note) sb0 ; extra command only for debugging (note) ? ? ? ld p0con, #11111111b ; p0.0?p0.3 a/d input mode ld p1conh, #00001111b ; p1.4?p1.5 a/d input mode ld p2conl, #11110000b ; p2.2?p2.3 a/d input mode ? ? ld adcon, #00000001b ; channel adc0, fxx, conversion start ad0_chk: tm adcon, #00001000b ; a/d conversion end ? eoc check jr z, ad0_chk ; no ld ad0bufh, addatah ; 8-bit conversion data ld ad0bufl, addatal ; 2-bit conversion data ? ? ld adcon, #00110001b ; channel adc3, fxx, conversion start ad3_chk: tm adcon, #00001000b ; a/d conversion end ? eoc check jr z, ad3_chk ; no ld ad3bufh, addatah ; 8-bit conversion data ld ad3bufl, addatal ; 2-bit conversion data ? ? note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 watch timer 17-1 17 watch timer overview watch timer functions include real-time and watch-time measurement and interval timing for the system clock. to start watch timer operation, set bit1 and bit 6 of the watch timer mode register, wtcon.1and 6, to ?1?. after the watch timer starts and elapses a time, the watch timer interrupt is automatically set to ?1?, and interrupt requests commence in 1.955 ms or 0.125, 0.25 and 0.5-second intervals. the watch timer can generate a steady 0.5 khz, 1 khz, 2 khz, or 4 khz signal to the buzzer output (bzout pin). by setting wtcon.3 and wtcon.2 to ?11b?, the watch timer will functi on in high-speed mode, generating an interrupt every 1.955 ms. high-speed mode is useful for timing events for program debugging sequences. ? real-time and watch-time measurement ? using a main system or subsystem clock source ? buzzer output frequency generator ? timing tests in high-speed mode
watch timer S3C84H5/f84h5 17-2 watch timer control register (wtcon: r/w) f8h wtcon.7 wtcon.6 wtcon.5 wtcon .4 wtcon.3 wtcon.2 wtcon.1 wtcon.0 reset "0" "0" "0" "0" "0" "0" "0" "0" table 17-1. watch timer c ontrol register (wtcon): se t 1, bank 1, f8h, r/w bit name values function address 0 select (fx/256) as the watch timer clock (fx: main clock) wtcon.7 1 select subsystem clock as watch timer clock 0 disable watch timer interrupt wtcon.6 1 enable watch timer interrupt 0 0 0.5 khz buzzer (bzout) signal output 0 1 1 khz buzzer (bzout) signal output 1 0 2 khz buzzer (bzout) signal output wtcon.5?.4 1 1 4 khz buzzer (bzout) signal output 0 0 set watch timer interrupt to 0.5 s. 0 1 set watch timer interrupt to 0.25 s. 1 0 set watch timer interrupt to 0.125 s. wtcon.3?.2 1 1 set watch timer interrupt to 1.955 ms. 0 disable watch timer, clear frequency dividing circuits wtcon.1 1 enable watch timer 0 interrupt is not pending, clear pending bit when write wtcon.0 1 interrupt is pending f8h note: main system clock frequency (fx) is assumed to be 9.8304 mhz
S3C84H5/f84h5 watch timer 17-3 watch timer circuit diagram wtcon.1 wtcon.2 wtcon.3 wtcon.4 wtcon.5 enable/disable selector circuit mux wtcon.0 wtint wtcon.6 buzzer output (bzout) f w /2 14 f w /2 13 f w /2 12 f w /2 6 f w /64 (0.5 khz) f w /32 (1 khz) f w /16 (2 khz) f w /8 (4 khz) 1 hz fx = main system clock (9.8304mhz) f xt = subsystem clock (32768 hz) fw = watch timer clock selector wtcon.7 frequency dividing circuit f w 32768 hz f xt fx/256 figure 17-1. watch ti mer circuit diagram
watch timer S3C84H5/f84h5 17-4 programming tip ? using the watch timer org 0000h vector 0d6h,wt_int org 0100h initial: di sb1 ; extra command only for debugging (note) ld 0f7h,#5fh ; extra command only for debugging (note) sb0 ; extra command only for debugging (note) ld imr,#00010000b ; enable irq3 interrupt ld sph,#00000000b ; set stack area ld spl,#0ffh ld btcon,#10100011b ; disable watch-dog ld wtcon,#11001110b ; 0.5 khz buzzer, 1.955ms duration interrupt ; interrupt enable, (fxt:32,768hz) ei main: ? ? ? main routine ? ? ? jr t,mian wt_int: ? ? ? and wtcon,#11111110b ; pending clear iret .end note : in debug mode, you have to include three extra commands in initial routine to operate ports correctly. if you omit these commands, port do not operate correctly. after you have finished your program and before assembling, you have to remove these three commands.
S3C84H5/f84h5 low voltage reset 18-1 18 low voltage reset overview the S3C84H5/f84h5 can be reset in four ways: ? by external power-on-reset ? by the external reset input pin pulled low ? by the digital watchdog timing out ? by the low voltage reset circuit (lvr) during an external power-on reset, the voltage vdd is high level and the nreset pin is forced low level. the nreset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this brings the S3C84H5/f84h5 into a known operating status. to ensure correct start-up, the user should take that reset signal is not released before the vdd level is sufficient to allow mcu operation at the chosen frequency. the nreset pin must be held to low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal cpu clock oscillation to stabilize. the minimu m required oscillation stabilization time for a reset is approximately 6.55 ms ( ? 2 16 /fosc, fosc= 10mhz). when a reset occurs during normal operation (with both vdd and nreset at high level), the signal at the nreset pin is forced low and the reset operation starts. all system and peripheral control registers are then set to their default hardware reset values (see table 8-1). the mcu provides a watchdog timer function in order to ensure graceful recovery from software malfunction. if watchdog timer is not refreshed before an end-of-counter conditio n (overflow) is reached, the internal reset will be activated. the S3C84H5/f84h5 has a built-in low voltage reset circuit that allows detection of power voltage drop of external v dd input level to prevent a mcu from malfunctioning in an unstable mcu power level. this voltage detector works for the reset operation of mcu. this low voltage reset includes an analog comparator and vref circuit. the value of a detection voltage is 2.8v. the on-chip low voltage reset, features static reset when supply voltage is below a reference voltage value (typical 2.8 v). thanks to this feature, external reset circuit can be removed while keeping the application safety. as long as the supply voltage is below the reference value, there is an internal and static reset. the mcu can start only when the supply voltage rises over the reference voltage. when you calculate power consumption, please remember that a static current of lvr circuit should be added a cpu operating current in any operating modes such as stop, idle, and normal run mode.
low voltage reset S3C84H5/f84h5 18 - 2 + - v ref bgr v dd v ref v in v dd longger than 1us n.f internal system nreset when the v dd level is lower than 2.8v comparator notes: 1. the target of voltage detection level is 2.8 v at v dd = 5 v 2. bgr is band gap voltage reference longger than 1us n.f nreset watchdog nreset figure 18-1. low volt age reset circuit note to program the dura tion of the oscillation stabil ization interval, yo u make the appropri ate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon.
S3C84H5/f84h5 mtp 19-1 19 mtp overview the s3f84h5 single-chip cmos microcontroller is the mtp (multi time programmable) version of the S3C84H5 microcontroller. it has an on-chip half flash rom instead of masked rom. the half flash rom is accessed by serial data format. the half flash rom can be rewritten up to 100 times. the s3f84h5 is fully compatible with the S3C84H5, in function, in d.c. electrical characteristics, and in pin configuration. because of its simple programming requirements, the s3f84h5 is ideal for use as an evaluation chip for the S3C84H5. test xt in xt out nreset av ss p3.0 p3.1 ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 32-sop 32-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 p3.3 p3.2 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3/ sclk p1.2/tacap/int2/ sdat p1.1/tack/buz/int1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref v ss figure 19-1. pin assignm ent (32-pin sop/sdip)
mtp S3C84H5/f84h5 19-2 v ss test xt in xt out nreset av ss p3.0 p3.1 ad0/p0.0 ad1/p0.1 p0.2/ad2 p0.3/ad3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 30-sdip 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3/ sclk p1.2/tacap/int2/ sdat p1.1/tack/buz/int1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref figure 19-2. pin assi gnment (30-pin sdip)
S3C84H5/f84h5 mtp 19-3 v ss test xt in xt out nreset av ss ad0/p0.0 ad1/p0.1 ad2/p0.2 ad3/p0.3 p1.0/taout/int0 S3C84H5 s3f84h5 (top view) 28-sop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd txd/p2.7 rxd/p2.6 sck/p2.5 so/p2.4 p2.3/ad7/si p2.2/ad4/t1out0 p2.1/t1cap0/pwm p2.0/t1ck0/tbpwm p1.5/ad6/t1cap1 p1.4/ad5/t1ck1 p1.3/t1out1/int3s/ sclk p1.2/tacap/int2/ sdat p1.1/tack/buz/int1 28 27 26 25 24 23 22 21 20 19 18 17 x out x in av ref figure 19-3. pin assi gnment (28-pin sop)
mtp S3C84H5/f84h5 19-4 table 19-1. descri ptions of pins used to read/write the flash rom main chip during programming pin name pin name pin no. i/o function p1.2 sdat 30 (32-pin) 28 (30-pin) 26 (28-pin) i/o serial data pin (output when reading, input when writing) input and push-pull output port can be assigned p1.3 sclk 31 (32-pin) 29 (30-pin) 27 (28-pin) i serial clock pin (input only pin) test vpp 4 i power supply pin for flash rom cell writing (indicates that mtp enters into the writing mode). when 12.5 v is applied, mtp is in writing mode and when 5 v is applied, mtp is in reading mode. (option) nreset nreset 7 i vdd/vss v dd /v ss 32/1 (32-pin) 30/1 (30-pin) 28/1 (28-pin) i logic power supply pin. table 19-2. comparison of s3 f84h5 and S3C84H5 features characteristic s3f84h5 S3C84H5 program memory 16 kbyte fl ash rom 16k byte mask rom operating voltage (v dd ) 2.8 v to 5.5 v 2.8 v to 5.5 v mtp programming mode v dd = 5 v, v pp = 12.5 v pin configuration 32 sdip/ sop, 30 sdip,28 sop eprom programmability user program mu lti time programmed at the factory
S3C84H5/f84h5 electrical data 20-1 20 electrical data overview in this chapter, S3C84H5/f84h5 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capacitance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? uart timing characteristics in mode 0 ? a/d converter electrical characteristics
electrical data S3C84H5/f84h5 20-2 table 20-1. absolute maximum ratings (t a = 25 c) parameter symbol c onditions rating unit supply voltage v dd ? ? 0.3 to + 6.5 input voltage v i all input ports ? 0.3 to v dd + 0.3 output voltage v o all output ports ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 all i/o pins active ? 60 one i/o pin active + 30 output current low i ol all i/o pins active + 200 ma operating temperature t a ? ? 25 to + 85 storage temperature t stg ? ? 65 to + 150 c table 20-2. input/o utput capacitance (t a = ? 25 c to 85 c, v dd = 0 v ) parameter symbol conditions min typ. max unit input capacitance c in output capacitance c out i/o capacitance c io f = 1 mhz; unmeasured pins are tied to v ss ? ? 10 pf
S3C84H5/f84h5 electrical data 20-3 table 20-3. d.c. electrical characteristics (t a = ? 25 c to + 85 c, 2.5v to 5.5 v) parameter symbol conditi ons min typ. max unit fx = 0 ? 8mhz, fxt = 32.8khz lvr off 2.5 5.5 fx = 0 ? 8mhz, fxt = 32.8khz lvr on lvr 5.5 operating voltage v dd fx = 0 ? 10mhz 4.5 5.5 v v ih1 v dd = 2.5v to 5.5 v all port and nreset 0.8 v dd input high voltage v ih2 v dd = 2.5v to 5.5 v x in and xt in v dd ? 0.5 ? v dd v v il1 v dd = 2.5v to 5.5 v all ports and nreset 0.2v dd input low voltage v il2 v dd = 2.5v to 5.5 v x in and xt in ? ? 0.4 v output high voltage v oh v dd = 5.0 v i oh = ? 2 ma all ports v dd ? 1.0 ? ? v v ol1 v dd = 5.0 v, i ol = 16 ma ports 0 and 4 output low voltage v ol2 v dd = 5.0 v, i ol = 4 ma ports 1, 2 and 3 ? 0.4 2.0 v i lih1 v in = v dd all input pins except i lih2 3 input high leakage current i lih2 v in = v dd x in , x out and xt in , xt out ? ? 20 i lil1 v in = 0 v all input pins except and i lil2 ? 3 input low leakage current i lil2 v in = 0 v x in , x out and xt in , xt out ? ? ? 20 output high leakage current i loh v out = v dd all output pins ? ? 3 output low leakage current i lol v out = 0 v all output pins ? ? ?3 a
electrical data S3C84H5/f84h5 20-4 table 20-3. d.c. electrical characteristic s (concluded) (t a = ? 25 c to + 85 c, v dd = 2.5 v to 5.5 v) parameter symbol conditi ons min typ. max unit r p1 v dd = 5 v; v in = 0 v t a = 25 c all i/o pins except nreset 25 50 100 pull-up resistor r p2 v dd = 5 v; v in = 0 v t a = 25 c resetb only 150 250 480 k ? v dd = 4.5 v to 5.5 v run mode 10 mhz cpu clock 5.0 10 i dd1(2) v dd = 2.5 v to 3.3 v run mode 4 mhz cpu clock ? 2.5 5.0 v dd = 4.5 v to 5.5 v idle mode 10 mhz cpu clock 2.0 4.0 i dd2 v dd = 2.5 v to 3.3 v idle mode 4 mhz cpu clock ? 1.0 2.0 ma i dd3 sub operating: main-osc stop v dd = 2.5 v to 3.3 v 32768 hz crystal oscillator ? 400 800 i dd4 sub idle mode: main-osc stop v dd = 2.5 v to 3.3 v 32768 hz crystal oscillator ? 300 600 supply current (1) i dd5(3) v dd = 4.5v to 5.5 v, t a =25 c, stop mode ? 150 400 ua notes : 1. supply current does not include current drawn through inte rnal pull-up resistors or external output current loads. 2. idd1 and idd2 include a power consumption of subsystem oscillator. 3. idd3 and idd4 are the current when the main system clock oscillation stop and the subsystem clock is used. 4. idd5 is the current when the main and subsystem clock oscillation stop. 5. all currents (idd1- idd5 ) include the current consumption of lvr circuit.(except the case that lvr is disabled) 6. idd5 is the same regardless of lvr on or lvr off.
S3C84H5/f84h5 electrical data 20-5 table 20-4. a.c. electrical characteristics (t a = ? 25 c to + 85 c, 2.5v to 5.5 v) parameter symbol conditi ons min typ. max unit interrupt input high, low width (ports 2) t inth , t intl v dd = 5 v 180 ? ? ns resetb input low width t rsl input 1.0 ? ? s note : user must keep more large value then min value. t intl 0.8 v dd 0.2 v dd t inth 0.2 v dd figure 20-1. input timing for ex ternal interrupts (ports 2) reset t rsl 0.2 v dd figure 20-2. input timing for reset
electrical data S3C84H5/f84h5 20-6 table 20-5. main osci llator frequency (f osc1 ) (t a = ? 25 c + 85 c, 2.5v to 5.5 v) oscillator clock circ uit test condition mi n typ. max unit main crystal or ceramic x in c1 c2 x out v dd = 2.5v to 5.5 v 1 ? 10 external clock (main system) x in x out v dd = 2.5v to 5.5 v 1 ? 10 mhz table 20-6. main oscillator clock stabilization time (t st1 ) (t a = ? 25 c + 85 c, 2.5v to 5.5 v) oscillator test conditi on min typ. max unit main crystal ? ? 10 main ceramic f osc > 400 khz; oscillation stabilizat ion occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms external clock (main system) x in input high and low width (t xh , t xl ) 50 ? ? ns t wait when released by a reset (1) ? 2 16 /f osc ? sec oscillator stabilization wait time t wait when released by an interrupt (2) ? ? ? sec notes: 1. f osc is the oscillator frequency. 2. the duration of the oscillator stabilization wait time, t wait , when it is released by an interrupt is determined by the settings in the basic timer control register, btcon.
S3C84H5/f84h5 electrical data 20-7 x in t xh t xl 1/f osc1 v dd - 0.5 v 0.4 v figure 20-3. clock timing measurement at x in table 20-7. sub oscillator frequency (f osc2 ) (t a = ? 25 c + 85 c, v dd = 2.5 to 5.5 v) oscillator clock circuit test condition min typ. max unit crystal c1 c2 xt in xt out r crystal oscillation frequency c1 = 100 pf, c2 = 100 pf r = 330 ? xt in and xt out are connected with r and c by soldering. 32 32.768 34 khz table 20-8. subsystem oscillator (crystal) stabilization time (t st2 ) (t a = 25 c) test condition min typ. max unit v dd = 4.5 v to 5.5 v ? 800 1600 ms v dd = 2.5 to 3.3 v ? 10 s note : oscillation stabilization time (t st2 ) is the time required for the oscillator to it?s normal oscillation when stop mode is released by interrupts.
electrical data S3C84H5/f84h5 20-8 table 20-9. data retention supply voltage in stop mode (t a = ? 25 c to + 85 c, 2.5vto 5.5 v) parameter symbol conditi ons min typ max unit data retention supply voltage v dddr stop mode 2.5 ? 5.5 v data retention supply current i dddr stop mode, v dddr = 2.7 v ? ? 8 a note : supply current does not include current drawn through inte rnal pull-up resistors or external output current loads. note: t wait is the same as 4096 x 16 x 1/f osc . execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilzation time data retention mode t wait reset v dd normal operating mode figure 20-4. stop mode relea se timing initiated by reset
S3C84H5/f84h5 electrical data 20-9 execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: t wait is the same as 4096 x 16 x bt clock figure 20-5. stop mode (main) rel ease timing initiated by interrupts execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: when the case of select the fxx/128 for basic timer input clock before enter the stop mode. twait = 128 x 16 x (1/32768) = 62.5 ms figure 20-6. stop mode (sub) releas e timing initiated by interrupts
electrical data S3C84H5/f84h5 20-10 table 20-10. uart timing characteristics in mode 0 (10 mhz) (t a = ? 25 c to + 85 c, 2.5v to 5.5 v, load capacitance = 80 pf) parameter symbol min typ. max unit serial port clock cycle time t sck 500 t cpu 6 700 output data setup to clock rising edge t s1 300 t cpu 5 ? clock rising edge to input data valid t s2 ? ? 300 output data hold after clock rising edge t h1 t cpu ? 50 t cpu ? input data hold after clock rising edge t h2 0 ? ? serial port clock high, low level width t high, t low 200 t cpu 3 400 ns notes : 1. all timings are in nanoseconds (ns) and assume a 10-mhz cpu clock frequency. 2. the unit t cpu means one cpu clock period. 0.2 v dd 0.8 v dd t high t low t sck figure 20-7. waveform for uart timing characteristics
S3C84H5/f84h5 electrical data 20-11 table 20-11. a/d converter electrical characteristics (t a = ? 25 c to + 85 c, 2.5v to 5.5 v, v ss = 0 v) parameter symbol test condi tions min typ. max unit resolution ? 10 ? bit total accuracy v dd = 5.12 v ? ? 3 integral linearity error ile cpu clock = 10 mhz av ref = 5.12 v ? 2 differential linearity error dle av ss = 0 v ? 1 offset error of top eot 1 3 offset error of bottom eob 0.5 2 lsb conversion time (1) t con 10-bit conversion 50 x 4/f osc (3) , f osc = 10 mhz 20 ? ? s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m ? analog reference voltage av ref ? 2.5 ? v dd analog ground av ss ? v ss ? v ss + 0.3 v analog input current i adin av ref = v dd = 5 v conversion time = 20 s ? ? 10 a av ref = v dd = 5 v conversion time = 20 s 1 3 av ref = v dd = 3 v conversion time = 20 s 0.5 1.5 ma analog block current (2) i adc av ref = v dd = 5 v when power down mode 100 500 na notes: 1. "conversion time" is the time required from the moment a conversion operation starts until it ends. 2. i adc is operating current during a/d conversion. 3. f osc is the main oscillator clock.
electrical data S3C84H5/f84h5 20-12 table 20-12. lvr(low voltage reset) circuit characteristics (t a = 25 c) parameter symbol test c ondition min typ max unit lvr voltage level v lvr lvr is enabled by smart option t a = 25 c 2.5 2.8 3.1 v cpu clock 1 mhz main oscillator frequency 1234567 supply voltage (v) 8 mhz 10 mhz 5.5 v minimum instruction clock = 1/4 oscillator clock 2.5 v figure 20-8. operat ing voltage range
S3C84H5/f84h5 electrical data 20-13 v dd v ss 104 S3C84H5/f84h5 figure 20-9. the circuit diagram to improve eft characteristics note : to improve eft characteristics, we recommend using power capacitor near S3C84H5/f84h5 like figure 20-9.
S3C84H5/f84h5 mechanical data 21-1 21 mechanical data overview the s3f84h5 is available in a 30-pin sdip package (samsung: 30-sdip-400) and a 32-pin sop package (32-sop-450a) and 32-pin sdip package(samsung: 32-sdip-400) and a 28-pin sop package (28-sop-375). package dimensions are shown in figures21-1, and 21-2 32-sop-450a #1 #16 #17 #32 2.40 max (0.43) 0.05 min 1.27 note: dimensions are in millimeters 19.90 0.2 0.40 0.1 12.00 0.3 2.00 0.2 11.43 0-8 8.34 0.2 0.78 0.2 0.20 + 0.1 - 0.05 figure 21-1. 32-sop-450 a package dimensions
mechanical data S3C84H5/f84h5 21-2 note: dimensions are in millimeters. 27.88 max 27.48 0.20 (1.37) 32-sdip-400 9.10 0.20 #32 #1 0.45 0.10 1.00 0.10 3.80 0.20 5.08 max 1.778 0.51 min 3.30 0.30 #17 #16 0-15 0 . 2 5 + 0 . 1 0 - 0 . 0 5 10.16 figure 21-2. 32-sdip-40 0 package dimensions
S3C84H5/f84h5 mechanical data 21-3 note: dimensions are in millimeters. 27.88max 27.48 0.2 1.778 (1.30) 0.51 min 3.30 0.3 3.81 0.2 5.08 max 0-15 1.12 0.1 0 . 2 5 + 0 .1 - 0 . 0 5 10.16 #30 #16 #15 #1 30-sdip-400 0.56 0.1 8.94 0.2 figure 21-3. 30-pin sdip package dimensions
mechanical data S3C84H5/f84h5 21-4 28-sop-375 #1 #14 #15 #28 note: dimensions are in millimeters 10.45 0.3 7.70 0.2 0.60 0.2 0.15 + 0.10 - 0.05 2.50 max (0.56) 0.05 min 17.62 0.2 0.41 0.1 2.15 0.1 18.02 max 1.27 9.53 8 figure 21-4. 28-sop-375 package dimensions
S3C84H5/f84h5 development tools 22-1 22 development tools overview samsung provides a powerful and easy-to-use development support system on a turnkey basis. the development support system is composed of a host system, debugging tools, and supporting software. for a host system, any standard computer that employs win95/98/2000 as its operating system can be used. a sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, smds2+ or sk-1000, for the s3c7-, s3c9-, and s3c8- microcontroller fa milies. smds2+ is a newly improved version of smds2, and sk-1000 is supported by a third party tool vendor. samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be easily sized, moved, scrolled, highlighted, added, or removed. sasm the sasm is a re-locatable assembler for samsung's s3c8-series microcontrollers. the sasm takes a source file containing assembly language statements and translates them into a corresponding source code, an object code and comments. the sasm supports macros and conditional assembly. it runs on the ms-dos operating system. as it produces the re-locatable object codes only, the user should link object files. object files can be linked with other object files and loaded into memory. sasm requires a source file and an auxiliary register file (device_name.reg) with device specific information. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generating an object code in the standard hexadecimal format. assembled program codes include the object code used for rom data and required in-circuit emulators program control data. to assemble programs, sama requires a source file and an auxilia ry definition (devic e_name.def) file with devi ce specific information. hex2rom hex2rom file generates a rom code from a hex file which is produced by the assembler. a rom code is needed to fabricate a microcontroller which has a mask rom. when generating a rom code (.obj file) by hex2rom, the value "ff" is automatically filled in to the unused rom ar ea, up to the maximu m rom size of the target device.
development tools S3C84H5/f84h5 22-2 target boards target boards are available for all the s3c8-series microcontrollers. all the required target system cables and adapters are included on the device-specific target board. tb84h5 is a specific target board for the S3C84H5/f84h5 development. bus emulator (smds2+ or sk-1000) rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam8 base unit power supply unit ibm-pc at or compatible tb84h5 target board eva chip target application system figure 22-1. smds+ or sk- 1000 product configuration
S3C84H5/f84h5 development tools 22-3 tb84h5 target board the tb84h5 target board is used for the S3C84H5 and the s3f84h5 microcontroller. it is supported by the smds2+ or sk-1000 development system (in-circuit emulator).figure 22-2. tb84h5 target board configuration tb84i9/8/84h5 gnd v cc to user_v cc off on smds2 smds2+ j101 42sdip j102 44qfp 1 5 15 21 10 42 40 25 22 30 35 1 5 15 22 10 44 40 30 23 35 25 20 p2 25 160 30 20 10 1 150 140 130 50 60 70 80 90 100 110 120 reset r1 d1 c1 c11 u2 r7 r8 y1 c7 cb + c9 c10 jp10 c2 c3 t1 t2 t3 t4 idle + stop + r5 r4 c12 20 10 1 51 76 26 rev.x '200x.xx.xx cn1 y2 ar1 c16 sw1 ar2 jp1 figure 22-2. s3f84i9/ s3 f84i8/s3f84h5 target board configuration
development tools S3C84H5/f84h5 22-4 table 22-1. power selecti on settings for tb84h5 to user_vcc' settings op erating mode comments to user_v dd off on target system smds2+ or sk-1000 tb84h5 v dd v ss v dd smds2+ or sk-1000 supplies v dd to the target board (evaluation chip) and the target system. to user_v dd off on target system smds2+ or sk-1000 tb84h5 external v dd v ss v dd smds2+ or sk-1000 supplies v dd only to the target board (evaluation chip). the target system must have a power supply of its own. table 22-2. using single header pins as the input path fo r external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led this led is on when the evaluation chip (s3e84i0) is in idle mode. stop led this led is on when the evaluation chip (s3e84i0) is in stop mode.
S3C84H5/f84h5 development tools 22-5 1 3 5 7 9 11 j102 44-pin dip socket 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 20 22 24 26 28 30 32 34 36 38 40 42 44 10 12 14 16 18 2 4 6 8 int1/buz/tack/p1.1 int3/t1out1/p1.3 v ss x in xtin nreset t1cap0/pwm/p2.1 ad5/t1ck1/p1.4 si/ad7/p2.3 sck/p2.5 tx/p2.7 avss p3.1 p3.3 p0.1/ad1 p0.3/ad3 int0/taout/p1.0 int2/tacap/p1.2 v dd x out test xtout tbpwm/t1ck0/p2.0 t1out0/ad4/p2.2 t1cap1/ad6/p1.5 so/p2.4 rx/p2.6 avref p3.0 p3.2 not used p0.0/ad0 p0.2/ad2 not used not used not used not used not used not used not used not used not used not used not used figure 22-3. 44-pin connector pin assignment for tb84h5
development tools S3C84H5/f84h5 22-6 1 3 5 7 9 11 j102 42 -pin dip socket 13 15 17 19 21 20 10 12 14 16 18 2 4 6 8 not used not used not used not used not used int1/buz/tack/p1.1 vdd vss xout xin test xtin xtout nreset not used tbpwm/t1ck0/p2.0 pwm/t1cap0/p2.1 t1out0/ad4/p2.2 int0/taout/p1.0 int3/t1out1/p1.3 int2/tacap/p1.2 ad3/p0.3 ad2/p0.2 ad1/p0.1 ad0/p0.0 not used not used not used not used not used not used p3.3 p3.2 p3.1 p3.0 avss avref p2.7/txd p2.6/rxd p2.5/sck p2.4/so p2.3/ad7/si 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 22-4. 42-pin connector pin assignment for tb84h5 target board 44-pin connector target system j101 12 43 44 part name: as20d order cods: sm6304 12 43 44 44-pin connector figure 22-5. tb84h5 adapter ca ble for 44pin connector package
(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8- series mask rom order form product description: device number: s3c8___- ________ (write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: ) for what kind of product will you be using this order? new model upgrade of an existing model replacement of an existing model others if you are replacing an existing model, please indicate the former product name ( ) ) what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same mcu before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager)
(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c8- series request for production at customer risk customer information: company name: ________________________________________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3c8___- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: ________________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: ______________________________ _______________________________________ (person placing the risk order) (sec sales representative)
(for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c84i8/c84i9 mask option selection form device number: s3c8___-________(write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ please answer the following questions: ) application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application

▲Up To Search▲

Price & Availability of S3C84H5

	To Download S3C84H5 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .